Programmable data width converter device, system and method thereof

1. A programmable data width converter (pDWC) comprising:

a control Finite State Machine (FSM) configured to receive input values of m and n, and control any or a combination of L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value) based on the received values of m and n, wherein the pDWC is configured to programmably convert width of ‘m’ k-bit word input to ‘n’ k-bit word output, and wherein 1≤m≤M and 1≤n≤N; and

a loadable programmable shift register with programmable load location (pSRL) operatively coupled with the control FSM, wherein the pSRL is configured to perform loading and shifting functions based on the L, S, LL, and p values loaded by the control FSM.

2. The converter of claim 1 , wherein the pSRL is loaded based on value of the LL and by setting L=1, and wherein the pSRL is shifted by setting S=1 in a manner such that data is loaded in m bits and read out in n bits.

3. The converter of claim 1 , wherein the pSRL is at least M+N bits wide.

4. The converter of claim 1 , wherein the p is equal to n.

5. The converter of claim 1 , wherein the load register width is M bits, and wherein m bits of said load register are used.

6. The converter of claim 1 , wherein the control FSM loads at least n bits into the pSRL that has width W where W≥(M+N), and wherein if m>n, only one load is required, else if m<n, multiple load cycles are required with S=0.

7. The converter of claim 6 , wherein the control FSM keeps a count C of bits that are currently in the pSRL, wherein each load increments the C by m such that when C≥n has been loaded into the pSRL, the control FSM initiates a shift that shifts out n bits and decrements C by n, and wherein when a load and shift happen together, (m−n) is added to C, and wherein whenever a free space exists in the pSRL as defined by (W−C)≥(m−n), the control FSM performs a load cycle, and wherein when L=S=1, loading happens while shifts are going on.

8. The converter of claim 1 , wherein the pDWC is a k-bit pDWC with the control FSM being operatively coupled with either a large pSRL allowing m and n to be integral multiples of k, or being operatively coupled to control k single-bit pSRLs in parallel.

9. The converter of claim 8 , wherein the pDWC requires a minimum of or equal to k×(M+N) number of flops.

10. The converter of claim 1 , wherein the pSRL is any of a right shift register or a left shift register.

11. The converter of claim 1 , wherein the LL defines where data D is loaded.

12. A method for programmably converting width of m k-bit word input into n k-bit word output by a programmable data width converter (pDWC), said method comprising:

receiving, by a control Finite State Machine (FSM), input values of m and n;

controlling, by the control FSM, any or a combination of L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value) based on the received values of m and n;

converting programmably, by the pDWC, width of ‘m’ k-bit word input to ‘n’ k-bit word output, and wherein 1≤m≤M and 1≤n≤N; and

performing, by a loadable programmable shift register with programmable load location (pSRL) operatively coupled with the control FSM, loading and shifting functions based on the L, S, LL, and p values loaded by the control FSM.

13. The method of claim 12 , wherein if load and shift happen together, (m−n), is added to C.