Ultra-responsive phase shifters for depletion mode silicon modulators
A novel phase shifter design for carrier depletion based silicon modulators, based on an experimentally validated model, is described. It is believed that the heretofore neglected effect of incomplete ionization will have a significant impact on ultra-responsive phase shifters. A low VπL product of 0.3 V·cm associated with a low propagation loss of 20 dB/cm is expected to be observed. The phase shifter is based on overlapping implantation steps, where the doses and energies are carefully chosen to utilize counter-doping to produce an S-shaped junction. This junction has a particularly attractive VπL figure of merit, while simultaneously achieving attractively low capacitance and optical loss. This improvement will enable significantly smaller Mach-Zehnder modulators to be constructed that nonetheless would have low drive voltages, with substantial decreases in insertion loss. The described fabrication process is of minimal complexity; in particular, no high-resolution lithographic step is required.
1. A method of fabricating an optical modulator device, comprising: a) providing a wafer with a semiconductor layer thereon; b) forming a rib waveguide structure in the semiconductor layer; c) implanting n-type and p-type dopants into the rib waveguide in multiple implantation steps to produce an n-type region on one side of the rib waveguide, a p-type region on another side of the rib waveguide region, and an overlap region therebetween with at least three layers alternating between n-type and p-type; and d) annealing the implanted rib waveguide structure; wherein step c) includes a counter-doping technique comprising several implant steps combining in a linear fashion to create pn junctions with nonlinear shapes in the rib waveguide for enabling optical modulation, whereby a first donor concentration of a first type of dopant exceeds a second donor concentration of a second type of dopant in top and bottom parts of the overlap region.
2. The method according to claim 1 , wherein the overlap region has a length dimension, and comprises a non-planar junction interface comprising an N and a P implantation overlap as viewed in cross section taken perpendicular to the length dimension, configured to increase a junction area between said n-type and said p-type layers per unit length of the length dimension of the junction.
3. The method according to claim 2 , wherein said non-planar junction interface comprises a shape geometry selected from the group consisting of “U”-shaped, “C”-shaped, and “S”-shaped.
4. The method according to claim 2 , wherein step c) includes forming the overlap region into a concave side of the non-planar junction interface with a first dopant type in a top and bottom of the overlap region, and a convex side of the non-planar junction interface with a second dopant type in a middle part of the overlap region.
5. The method according to claim 1 , wherein step c) includes:
i) masking the n-type region;
ii) implanting p-type dopants into the p-type region and the overlap region;
iii) masking the p-type region; and
iv) implanting n-type dopants into the n-type region and the overlap region.
6. The method according to claim 5 , wherein one of step ii) or step iv) includes a first lower energy step to implant dopant at a top of the rib waveguide, and a second higher energy step to implant dopant at a bottom of the rib waveguide; and wherein the other of step ii) or step iv) includes an intermediate energy step to implant dopant in a middle of the overlap region.
7. The method according to claim 1 , wherein the n-type region and the p-type region on each side of the rib waveguide are at least 50 nm wide.
8. The method according to claim 1 , wherein step b) also includes forming a slab waveguide on either side of the rib waveguide; and
wherein step c) includes:
doping the slab waveguide adjacent to the n-type region to form an n-type contact; and
doping the slab waveguide adjacent to the p-type region to form an p-type contact.
9. The method according to claim 8 , wherein step b) includes forming the rib waveguide and the slab waveguide from the semiconductor layer by an anisotropic etch.
10. The method according to claim 8 , further comprising depositing a thin layer of an insulator conformally on top of the rib and slab waveguides.
11. The method according to claim 1 , wherein said wafer comprises a silicon-on-insulator wafer.
12. The method according to claim 1 , wherein step d) comprises rapid thermal annealing (RTA).