STRAINED SEMICONDUCTOR-ON-INSULATOR BY DEFORMATION OF BURIED INSULATOR INDUCED BY BURIED STRESSOR

1 . A device structure comprising:

a semiconductor substrate having first and second walls of one or more trench isolation structures extending partially into the substrate, a substrate interface region extending between the first and second walls;

a buried stressor structure on the substrate interface region and extending over a lateral extent between the first and second walls, the buried stressor structure having in-plane compressive stress;

a buried insulation layer comprising silicon dioxide over the buried stressor structure;

a thin upper semiconductor layer over the buried insulation layer, the thin upper semiconductor layer extending between the first and second walls and having in-plane tensile strain induced within a first portion of the thin upper semiconductor layer extending between the first and second walls, the strain induced by deformation of the buried insulation layer; and

an integrated circuit device having an active region at least partially in the first portion of the thin upper semiconductor layer,

wherein the deformation of the buried insulation layer is caused by edge relaxation of the buried stressor structure.

2 . The device structure of claim 1 , wherein the buried insulation layer comprises silicon dioxide with a thickness between 5 nm and 80 nm.

3 . The device structure of claim 1 , wherein the buried stressor structure comprises compressively strained silicon germanium alloy grown epitaxially on the substrate.

4 . The device structure of claim 1 , wherein the buried stressor structure comprises compressively strained silicon nitride.

5 . The device structure of claim 1 , wherein the thin upper semiconductor layer comprises silicon.

6 . The device structure of claim 1 , wherein the thin upper semiconductor layer comprises at least one of: silicon germanium, germanium, germanium tin, or another alloy of germanium, a group IV semiconductor, a semiconducting alloy, a compound of group IV elements, a II-VI compound semiconductor , and a III-V compound semiconductor.

7 . The device structure of claim 1 , wherein the thin upper semiconductor layer has a thickness between 0.2 nm and 50 nm.

8 . The device structure of claim 1 , further comprising a gate dielectric layer on the thin upper semiconductor layer separating the thin upper semiconductor layer from a gate electrode such that the upper surface of the thin semiconductor layer extending between the first and second walls provides at least a part of a channel region of a MOS transistor.

9 . The device structure of claim 8 , wherein partial relaxation within the buried insulation layer is non-uniform over a lateral extent between the first and second walls.

10 . The device structure of claim 9 , wherein the lateral extent between the first and second walls is less than 500 nm.

11 . The device structure of claim 1 , wherein the thin semiconductor layer is silicon and a surface of the thin semiconductor layer has in-plane tensile strain along two perpendicular directions.

12 . A method of manufacturing a device in a layered structure in which an upper thin semiconductor layer is disposed over a buried insulator layer and a buried compressively strained stressor layer under the buried insulator layer, the compressively strained stressor layer disposed on an underlying semiconductor substrate, the method comprising:

etching through the upper thin semiconductor layer, the buried insulator layer, the buried compressively strained stressor layer, and into the underlying substrate in a pattern defined by a mask layer, thereby at least partially relaxing the buried compressively strained stressor layer and causing deformation of the buried insulator layer, the deformation of the buried insulator layer inducing tensile strain in an upper surface of the thin semiconductor layer across at least a first portion of a lateral extent of the thin semiconductor layer between walls of one or more trenches formed by the etching; and

forming an active region of the device in the first portion of the surface semiconductor layer.

13 . The method of claim 12 , wherein the tensile strain induced in the upper surface of the thin semiconductor layer is uniaxial tensile strain.

14 . The method of claim 12 , wherein the tensile strain induced in the upper surface of the thin semiconductor layer is biaxial tensile strain.

15 . The method of claim 12 , wherein inducing tensile strain in the buried insulator layer produces the deformation of the buried insulator layer.

16 . The method of claim 12 , wherein the buried insulator layer comprises silicon dioxide

17 . The method of claim 12 , wherein the thin semiconductor layer is one of: silicon, silicon germanium, germanium, germanium tin, or another alloy of germanium, a group IV semiconductor, a semiconducting alloy, a compound of group IV elements, a II-VI compound semiconductor, and a III-V compound semiconductor.

18 . The method of claim 12 , wherein the buried stressor layer comprises an in-plane compressively stressed silicon germanium layer and the substrate consists essentially of silicon.

19 . The method of claim 12 , wherein the buried insulator layer is coupled to the buried stressor layer through a wafer bonding process.

20 . The method of claim 12 , wherein the tensile strain within the top surface of thin semiconductor layer is non-uniform over the lateral extent of the thin semiconductor layer.