IP Library Granted Patent US 10,510,883
Granted Patent B2
US 10,510,883 · App. 15/880,465 · Granted Dec 17, 2019

Asymmetric source and drain structures in semiconductor devices

Inventors: Yu-Lien Huang (Jhubei, TW); Peng Wang (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L29/7835H01L21/0228H01L21/02274H01L21/3065H01L21/311H01L21/3212H01L21/76829H01L29/6681H01L29/66659
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Quick Facts
Patent No.
US 10,510,883
App. No.
15/880,465
Granted
Dec 17, 2019
Kind
B2
Abstract

The present disclosure provides semiconductor devices with asymmetric source/drain structures. In one example, a semiconductor device includes a first group of source/drain structures on a first group of fin structures on a substrate, a second group of source/drain structures on a second group of fin structures on the substrate, and a first gate structure and a second gate structure over the first and the second group of fin structures, respectively, the first and second groups of source/drain structures being proximate the first and second gate structures, respectively, wherein the first group of source/drain structures on the first group of fin structures has a first source/drain structure having a first vertical height different from a second vertical height of a second source/drain structure of the second group of source/drain structures on the second group of fin structures.

Claims (39)

1. A method for forming a semiconductor device, comprising:

etching a first and a second source/drain structures on a first and a second fin structures in a first and a second active region, respectively, on a substrate by an etching gas mixture including a sulfur containing passivation gas, wherein the etching gas mixture etches the first source/drain structure at a faster etching rate than etching the second source/drain structure, the etching forming the first source/drain structure in the first active region having a first vertical height less than a second vertical height formed in the second source/drain structure in the second active region, wherein the first source/drain structure is n-type and the second source/drain structure is p-type.

2. The method of claim 1 , wherein the sulfur containing passivation gas selectively reacts with the second source/drain structure in the second active region, forming a passivation layer on the second source/drain structure while patterning the first source/drain structure in the first active region.

3. The method of claim 2 , wherein the sulfur containing passivation gas is carbonyl sulfide.

4. The method of claim 1 , further comprising:

prior to etching the first and the second source/drain structures, forming a third source/drain structure neighboring the first source/drain structure in the first active region, and forming a fourth source/drain structure neighboring the second source/drain structure in the second active region, wherein the third source/drain structure has a third vertical height greater than a fourth vertical height of the fourth source/drain structure.

5. The method of claim 4 , wherein a first step height is defined between the third vertical height and the first vertical height in the first active area, and a second step height is defined between the fourth vertical height and the second vertical height in the second active area, wherein the first step height is at least about 5% higher than the second step height.

6. The method of claim 1 , wherein the etching gas mixture comprises a carbon fluorine gas, an oxygen containing gas, and a carbonyl sulfide gas.

7. The method of claim 1 , wherein the etching gas mixture comprises carbon fluorine gas.

8. A method for forming a semiconductor device, the method comprising:

forming a first fin on a substrate;

forming a second fin on the substrate;

epitaxially growing a first source/drain region on the first fin;

epitaxially growing a second source/drain region on the second fin, wherein the first source/drain region has a first vertical height greater than a second vertical height of the second source/drain region;

forming a first dielectric layer over the first source/drain region and the second source/drain region; and

etching the first dielectric layer, the first source/drain region and the second source/drain region, wherein the etching etches the first source/drain region at a faster rate than the second source/drain region, wherein the etching exposes an outer sidewall of the first source/drain region.

9. The method of claim 8 , wherein after etching the first source/drain region has a first step height greater than a second step height of the second source/drain region.

10. The method of claim 9 , wherein a ratio of the first step height to the second step height is greater than 1.1.

11. The method of claim 10 , wherein the first vertical height is 8% to 20% greater than the second vertical height.

12. The method of claim 8 , wherein the first source/drain region is n-type and the second source/drain region is p-type.

13. The method of claim 8 , wherein etching is performed using a carbon fluorine gas, an oxygen containing gas, an inert gas, and a passivation gas.

14. The method of claim 13 , wherein:

the carbon fluorine gas is CF 4 ,

the oxygen containing gas is O 2 ,

the inert gas is Ar, and

and the passivation gas is COS.

15. A method for forming a semiconductor device, the method comprising:

forming a first fin on a substrate;

forming a second fin on the substrate;

epitaxially growing a first source/drain region on the first fin;

epitaxially growing a second source/drain region on the second fin;

forming a first dielectric layer over the first source/drain region and the second source/drain region;

forming a first opening and a second opening in the first dielectric layer, wherein forming the first opening and the second opening comprises etching the first dielectric layer, the first source/drain region and the second source/drain region, wherein the etching etches the first source/drain region at a faster rate than the second source/drain region; and

forming a first contact in the first opening and a second contact in the second opening, wherein a first contact area between the first contact and the first source/drain region is greater than a second contact area between the second contact and the second source/drain region, wherein the first contact has a point that abuts the first source/drain region, the point being above the first fin, wherein the first contact extends laterally from the point to an outermost edge of the first source/drain region in a direction perpendicular to the first fin.

16. The method of claim 15 , wherein, after forming the first opening and the second opening, a first step height of the first source/drain region is greater than a second step height of the second source/drain region.

17. The method of claim 16 , wherein, prior to forming the first opening and the second opening, a first vertical height of the first source/drain region is greater than a second vertical height of the second source/drain region.

18. The method of claim 15 , forming the first opening and the second opening comprises etching using a sulfur containing gas.

19. The method of claim 18 , wherein forming the first opening and the second opening forms a passivation layer over the second source/drain region while etching the first source/drain region.

20. The method of claim 15 , wherein after forming the first opening and the second opening, a first height of remaining portions of the first source/drain region is less than a second height of remaining portions of the second source/drain region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2018
From: HUANG, YU-LIEN; WANG, PENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 045257/0343 →
Continuity (2)
Provisional Application 62591265 · Nov 28, 2017
Related Publication 20190165171A1 · May 30, 2019