Power amplifier, power amplification method, and power amplification control apparatus and method

1. A device comprising:

a power amplifier, the power amplifier comprising n Doherty power amplifiers and an n-way outphasing combiner, wherein the n Doherty power amplifiers are connected in parallel, wherein n≥2 and n is an integer;

wherein each of the n Doherty power amplifiers comprises one input end and one output end;

wherein the n-way outphasing combiner comprises n input ends and one output end;

wherein the output ends of the n Doherty power amplifiers are separately connected to a respective one of the n input ends of the n-way outphasing combiner;

wherein each of the n Doherty power amplifiers has a respective power threshold; and

wherein the power amplifier is configured to:

when an input signal received on each of the n Doherty power amplifiers is less than the respective power threshold and the input signal is outphasing, operate the n-way outphasing combiner in an outphasing working state,

when an input signal received on each of the n Doherty power amplifiers is less than the respective power threshold and the input signal is non-outphasing, operate the n-way outphasing combiner in a non-outphasing working state,

when an input signal received on each of the n Doherty power amplifiers is greater than the respective power threshold and the input signal is outphasing, operate the n-way outphasing combiner in an outphasing working state, and

when an input signal received on each of the n Doherty power amplifiers is greater than the respective power threshold and the input signal is non-outphasing, operate the n-way outphasing combiner in a non-outphasing working state.

2. The device according to claim 1 ,

wherein each of the n Doherty power amplifiers is an m-way Doherty power amplifier, the m-way Doherty power amplifier comprising one primary power amplifier and m−1 peak power amplifiers, wherein m≥2 and m is an integer;

wherein the value of m in each of the n Doherty power amplifiers may have a same value or different value; and

wherein, in each m-way Doherty power amplifier, the primary power amplifier is connected in parallel to each peak power amplifier, and the m−1 peak power amplifiers are each connected in parallel.

3. The device according to claim 2 ,

wherein a first amplifier of the n Doherty power amplifiers is an m1-way Doherty power amplifier where m of the first amplifier equals m1, and wherein a second amplifier of the n Doherty power amplifiers is an m2-way Doherty amplifier, where m of the second amplifier equals m2, where m1 is not equal to m2.

4. The device according to claim 2 ,

wherein each m-way Doherty power amplifiers is a two-way symmetric Doherty power amplifier, the two-way symmetric Doherty power amplifier comprising one primary power amplifier and one peak power amplifier, and transistors having a same power are used in the primary power amplifier and the peak power amplifier; or

wherein each m-way Doherty power amplifier is a two-way asymmetric Doherty power amplifier, the two-way asymmetric Doherty power amplifier comprising one primary power amplifier and one peak power amplifier, and transistors having different powers are used in the primary power amplifier and the peak power amplifier.

5. The device according to claim 1 , wherein the n-way outphasing combiner is an Chireix combiner.

6. An apparatus comprising:

a power amplifier, the power amplifier comprising n Doherty power amplifiers, wherein n≥2 and n is an integer, wherein each of then Doherty power amplifiers comprises one input end and one output end;

a processor of a signal control system, the signal control system configured to provide n input signals to the power amplifier; and

a computer-readable storage medium storing a program to be executed by the processor, the program including instructions for:

determining, according to a working mode of the power amplifier, a power threshold corresponding to the power amplifier;

adjusting, when power levels of the n input signals reach the power threshold, the n input signals to n non-outphasing input signals or n outphasing input signals; and

controlling a transceiver to send the n adjusted input signals separately to the input ends of the Doherty power amplifiers.

7. The apparatus according to claim 6 , wherein the working mode of the power amplifier is a first working mode, and the corresponding power threshold is a first power threshold, wherein the first power threshold is greater than an initial working power of each peak power amplifier in each Doherty power amplifier; and

the program further includes instructions for adjusting, when the power levels of the n input signals reach the first power threshold, the n input signals to the n outphasing input signals.

8. The apparatus according to claim 7 , wherein the program further includes instructions for adjusting, when the power levels of the n input signals do not reach the first power threshold, the n input signals to the n non-outphasing input signals.

9. The apparatus according to claim 6 , wherein the working mode of the power amplifier is a second working mode, and the corresponding power threshold is a second power threshold, wherein the second power threshold is less than an initial working power of each peak power amplifier in each Doherty power amplifier; and

the program further includes instructions for adjusting, when the power levels of the n input signals reach the second power threshold, the n input signals to the n non-outphasing input signals.

10. The apparatus according to claim 9 , wherein the program further includes instructions for adjusting, when the power levels of the n input signals do not reach the second power threshold, the n input signals to the n outphasing input signals.

11. The apparatus according to claim 6 ,

wherein each of the n Doherty power amplifiers is an m-way Doherty power amplifier, the m-way Doherty power amplifiers comprising m power amplifiers, wherein the m power amplifiers include one primary power amplifier and m−1 peak power amplifiers, wherein m≥2 and m is an integer;

wherein the value of m in each of the n Doherty power amplifiers may have a same value or different value; and

wherein, in each m-way Doherty power amplifier, the primary power amplifier is connected in parallel to each peak power amplifier, and the m−1 peak power amplifiers are each connected in parallel.

12. The apparatus according to claim 11 , wherein the n non-outphasing input signals or the n outphasing input signals are associated with a Chireix combiner.

13. The apparatus according to claim 11 ,

wherein each m-way Doherty power amplifier is a two-way symmetric Doherty power amplifier, the two-way symmetric Doherty power amplifier comprising one primary power amplifier and one peak power amplifier, and transistors having a same power are used in the primary power amplifier and the peak power amplifier; or

wherein each m-way Doherty power amplifier is a two-way asymmetric Doherty power amplifier, the two-way asymmetric Doherty power amplifier comprising one primary power amplifier and one peak power amplifier, and transistors having different powers are used in the primary power amplifier and the peak power amplifier.

14. A method, comprising:

receiving a plurality of input signals at input ends of a plurality of Doherty power amplifiers;

triggering each amplifier of the plurality of Doherty power amplifiers to be in a working state according to a power level of a corresponding input signal of the plurality of input signals; and

triggering an outphasing combiner to be in a working state according to the power level of the corresponding input signal of the plurality of input signals, wherein the triggering includes that when the power levels of the plurality of input signals are less than a first power threshold and when the input signals are non-outphasing, the outphasing combiner is triggered to be in a non-outphasing working state, wherein the outphasing combiner is coupled to output ends of the plurality of Doherty power amplifiers.

15. The method of claim 14 , wherein each of the plurality of Doherty power amplifiers comprises a primary power amplifier and at least one peak power amplifier.

16. The method of claim 15 , wherein the primary power amplifier and the at least one peak power amplifier in each Doherty power amplifiers are triggered to be in a working state, and wherein the non-outphasing working state is where the input signals are received by the plurality of Doherty power amplifiers without being phase adjusted.

17. The method of claim 16 , wherein the triggering further includes that, when the power levels of the plurality of input signals are greater than the first power threshold and when the input signals are outphasing, the primary power amplifier and the at least one peak power amplifier in each Doherty power amplifier are triggered to be in a working state, and the outphasing combiner is triggered to be in an outphasing working state, wherein the outphasing working state is where the input signals are received by the plurality of Doherty power amplifiers after being phase adjusted.

18. The method of claim 15 , wherein each of the plurality of Doherty power amplifiers comprises one input end and one output end, wherein each of the plurality of Doherty power amplifiers are connected in parallel, wherein a total number of power amplifiers in each of the plurality of Doherty power amplifiers is m, wherein the m power amplifiers include one primary power amplifier and m−1 peak power amplifiers, wherein m≥2 and m is an integer m.

19. The method of claim 18 , wherein a value of m for a first amplifier of the plurality of Doherty power amplifiers is different than a value of m for a second amplifier of the plurality of Doherty power amplifiers.

20. The method of claim 15 , wherein each of the plurality of Doherty power amplifiers is a two-way symmetric Doherty power amplifier, or wherein each of the plurality of Doherty power amplifiers is a two-way asymmetric Doherty power amplifier.