Semiconductor device and semiconductor apparatus

1. A semiconductor device, comprising:

a first circuit structure, having a first line terminal;

a second circuit structure, having a second line terminal, wherein the first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap; and

a first conductive structure, formed in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal,

wherein the first circuit structure has a symmetric layout, the second circuit structure is a connection port and connected to the first circuit structure through the first conductive structure.

2. The semiconductor device of claim 1 , wherein the first circuit structure and the second circuit structure are electrically connected through the first conductive structure, so to form a statistic random access memory (SRAM) cell, wherein the first line terminal is a first gate line terminal, the second line terminal is a second gate line terminal.

3. The semiconductor device of claim 2 , wherein the first circuit structure comprises a 6-tranststor (6T) SRAM structure, and the second circuit structure is a single read port, having two transistors.

4. The semiconductor device of claim 2 , wherein the first circuit structure comprises a 6-tranststor (6T) SRAM structure, and the second circuit structure has multiple connection ports, each of the connection ports is electrically connected to the first gate line terminal of the first circuit structure through the first conductive structure.

5. The semiconductor device of claim 2 , wherein the first circuit structure further comprises a third gate line terminal, to be electrically connected to an adjacent SRAM cell, wherein the second circuit layer further comprises a second conductive structure electrically connecting the third gate line terminal of the SRAM cell and the adjacent SRAM cell.

6. The semiconductor device of claim 1 , wherein the first circuit structure and the second circuit structure respectively comprise a plurality of fin field effect transistors.

7. The semiconductor device of claim 6 , wherein the first circuit structure has a symmetric layout, the second circuit structure is a connection port and electrically connected to the first circuit structure through the first conductive structure.

8. The semiconductor device of claim 7 , wherein the first circuit structure and the second circuit structure are electrically connected through the first conductive structure, so to form a statistic random access memory (SRAM) cell, wherein the first line terminal is a first gate line terminal, the second line terminal is a second gate line terminal.

9. The semiconductor device of claim 8 , wherein the first circuit structure comprises a 6-tranststor (6T) SRAM structure, wherein the second circuit structure has a single connection port or the second circuit structure has multiple connection ports, each connection port is electrically connected to the first gate line terminal of the first circuit structure through the first conductive structure.

10. The semiconductor device of claim 8 , wherein the first circuit structure further comprises a third gate line terminal, to be electrically connected to an adjacent SRAM cell, wherein the second circuit layer further comprises a second conductive structure electrically connecting the third gate line terminal of the SRAM cell and the adjacent SRAM cell.

11. The semiconductor device of claim 1 , wherein the first conductive structure is a conductive plug.

12. A semiconductor apparatus, comprising:

a substrate, having a plurality of fin lines, formed by a protruding portion of the substrate, wherein the fin lines are extending along a first direction;

a plurality of gate line segments, crossing over the fin lines of the substrate, wherein the gate line segments are configured into multiple parallel lines, extending along a second direction perpendicular to the first direction; and

a conductive structure, disposed above or under adjacent two of the gate line segments, so to electrically connect the adjacent two of the gate line segments,

wherein the semiconductor apparatus is a statistic random access memory (SRAM) apparatus, comprises a plurality of SRAM cells, each SRAM cell is accordingly formed by the gate line segments, the fin lines and the conductive structure.

13. The semiconductor apparatus of claim 12 , wherein each SRAM cell comprises a first circuit structure and a second circuit structure electrically connected by the conductive structure, each of the first circuit structure and the second circuit structure comprises a plurality of fin field effect transistors.

14. The semiconductor apparatus of claim 13 , wherein the first circuit structure has a symmetric layout, the second circuit structure is a connection port and connected to the first circuit structure through the first conductive structure.

15. The semiconductor apparatus of claim 13 , wherein the first circuit structure and the second circuit structure are electrically connected through the conductive structure, so to form a corresponding one of the SRAM cells.

16. The semiconductor apparatus of claim 13 , wherein the first circuit structure comprises a 6-tranststor (6T) SRAM structure, and the second circuit structure is a single read port, having two transistors.

17. The semiconductor apparatus of claim 13 , wherein the first circuit structure comprises a 6-tranststor (6T) SRAM structure, and the second circuit structure has multiple connection ports, each of the connection ports is electrically connected to the first circuit structure through the first conductive structure.

18. The semiconductor apparatus of claim 12 , wherein the first conductive structure is a conductive plug.