Semiconductor device, display panel, display device, input/output device, and data processing device

1. A semiconductor device comprising:

a first D/A converter circuit; and

an amplifier electrically connected to the first D/A converter circuit, the amplifier comprising:

a first transconductance amplifier electrically connected to a first terminal, a second terminal, a first node, and a second node;

a current/voltage converter circuit between the first node and a third node, and between the second node and the third node;

a switch between the third node and the second terminal; and

an offset adjustment circuit electrically connected to the first node, the second node, and the third node,

wherein the first transconductance amplifier is configured to supply a first current to the first node and the second node on the basis of a voltage between the first terminal and the second terminal,

wherein the offset adjustment circuit is configured to supply a correction current to the first node and the second node, and

wherein the current/voltage converter circuit is configured to supply a first voltage to the third node on the basis of the first current and the correction current.

2. The semiconductor device according to claim 1 , wherein the switch is configured to control an electrical connection between the third node and the second terminal on the basis of an output enable signal.

3. The semiconductor device according to claim 1 , wherein a potential of the third node is made closer to a potential of the second terminal by the correction current supplied from the offset adjustment circuit.

4. The semiconductor device according to claim 1 ,

wherein the offset adjustment circuit comprises:

a register;

a second D/A converter circuit electrically connected to the register;

a switching circuit electrically connected to the register and the second D/A converter circuit; and

a second transconductance amplifier electrically connected to the switching circuit and cascode-connected to the first node and the second node,

wherein the register is configured to supply offset data to the switching circuit,

wherein the switching circuit is configured to supply a correction voltage to the second transconductance amplifier on the basis of the offset data and a voltage supplied from the second D/A converter circuit, and

wherein the second transconductance amplifier is configured to supply the correction current to the first node and the second node.

5. The semiconductor device according to claim 1 ,

wherein the offset adjustment circuit comprises:

a register configured to be supplied with an offset adjustment signal and a latch signal; and

a level shifter between the third node and the register,

wherein the level shifter is configured to supply the latch signal to the register on the basis of an output enable signal,

wherein the register is configured to supply the offset adjustment signal when the register is in a passage state,

wherein the register is configured to retain, as offset data, the offset adjustment signal on the basis of the latch signal, and

wherein the register is configured to supply the offset data when the register is in a non-passage state.

6. The semiconductor device according to claim 1 , further comprising a terminal region comprising a plurality of terminals,

wherein one of the plurality of terminals is electrically connected to the second terminal.

7. The semiconductor device according to claim 1 , further comprising:

a terminal region comprising a plurality of terminals; and

a buffer amplifier comprising a third terminal and a fourth terminal,

wherein the first terminal is electrically connected to a first output terminal of the first D/A converter circuit,

wherein the second terminal is electrically connected to one of the plurality of terminals,

wherein the third terminal is electrically connected to a second output terminal of the first D/A converter circuit, and

wherein the fourth terminal is electrically connected to another one of the plurality of terminals.

8. A display panel comprising:

the semiconductor device according to claim 1 ; and

a display region comprising a signal line,

wherein the signal line is electrically connected to the second terminal of the semiconductor device.

9. A display panel comprising:

the semiconductor device according to claim 1 ;

a display region comprising a signal line;

a buffer amplifier comprising a fifth terminal and a sixth terminal; and

a third D/A converter circuit electrically connected to the fifth terminal,

wherein the signal line is electrically connected to the second terminal of the semiconductor device and the sixth terminal of the buffer amplifier.

10. A display device comprising:

a display panel comprising the semiconductor device according to claim 1 and a display region comprising a signal line; and

a control portion configured to supply image data and control data to the display panel,

wherein the signal line is electrically connected to the second terminal of the semiconductor device.

11. An input/output device comprising:

the semiconductor device according to claim 1 ;

a display region comprising a signal line; and

an input portion comprising a sensing region,

wherein the signal line is electrically connected to the second terminal of the semiconductor device.

12. A data processing device comprising:

the semiconductor device according to claim 1 ;

a display region comprising a signal line; and

at least one of a keyboard, a hardware button, a pointing device, a touch sensor, an illuminance sensor, an imaging device, an audio input device, an eye-gaze input device, and an attitude determination device,

wherein the signal line is electrically connected to the second terminal of the semiconductor device.