Covergroup network analysis

1. A method comprising:

performing functional verification on a circuit design describing an electronic device;

based on the results of the functional verification of the circuit design, determining, by a computing system, occurrences of coverpoints within a covergroup, wherein each coverpoint corresponds to a signal state or a variable value in the circuit design during the functional verification; and

generating, by the computing system, a graphical presentation of the covergroup, wherein the graphical presentation include nodes, at least a subset of which correspond to the coverpoints, and wherein the nodes are clustered in the graphical presentation based, at least in part, on the occurrences of the coverpoints during the functional verification of the circuit design.

2. The method of claim 1 , further comprising determining, by the computing system, occurrences of coverage crosses in the covergroup based, at least in part, on the results of the functional verification of the circuit design, wherein each of the coverage crosses corresponds to a different plurality of the coverpoints occurring concurrently.

3. The method of claim 2 , wherein another subset of the nodes in the graphical presentation of the covergroup corresponds to the coverage crosses, and wherein the nodes are arranged in the graphical presentation of the covergroup based, at least in part, on a connectivity between the coverpoints and the coverage crosses.

4. The method of claim 1 , wherein generating the graphical presentation of the covergroup is performed by the computing system with a force-directed graph drawing algorithm.

5. The method of claim 1 , further comprising:

determining, by the computing system, a rank of the coverpoints based, at least in part, on the occurrences of the coverpoints during the functional verification of the circuit design; and

annunciating, by the computing system, the rank of one of the coverpoints in a corresponding node of the graphical presentation of the covergroup.

6. The method of claim 1 , further comprising:

identifying, by the computing system, at least one node cluster in the graphical presentation of the covergroup to filter; and

selectively removing, by the computing system, one or more nodes from the selected node cluster in the graphical presentation of the covergroup based, at least in part, on at least one of a coverage of the nodes, a cardinality associated with the nodes, or a distance between the coverpoints corresponding to the nodes.

7. The method of claim 1 , wherein performing functional verification on the circuit design describing the electronic device further comprises:

generating test stimulus to provide to the electronic device modeled in a verification environment based on the circuit design; and

recording the coverpoints performed by the electronic device in response to the test stimulus.

8. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

identifying results of functional verification performed on a circuit design describing an electronic device;

determining occurrences of coverpoints within a covergroup based on the results of the functional verification of the circuit design, wherein each coverpoint corresponds to a signal state or a variable value in the circuit design during the functional verification; and

generating a graphical presentation of the covergroup, wherein the graphical presentation include nodes, at least a subset of which correspond to the coverpoints, and wherein the nodes are clustered in the graphical presentation based, at least in part, on the occurrences of the coverpoints during the functional verification of the circuit design.

9. The apparatus of claim 8 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising determining occurrences of coverage crosses in the covergroup based, at least in part, on the results of the functional verification of the circuit design, and wherein each of the coverage crosses corresponds to a different plurality of the coverpoints occurring concurrently.

10. The apparatus of claim 9 , wherein another subset of the nodes in the graphical presentation of the covergroup corresponds to the coverage crosses, and wherein the nodes are arranged in the graphical presentation of the covergroup based, at least in part, on a connectivity between the coverpoints and the coverage crosses.

11. The apparatus of claim 8 , wherein generating the graphical presentation of the covergroup is performed by the computing system with a force-directed graph drawing algorithm.

12. The apparatus of claim 8 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising

determining a rank of the coverpoints based, at least in part, on the occurrences of the coverpoints during the functional verification of the circuit design; and

annunciating the rank of one of the coverpoints in a corresponding node of the graphical presentation of the covergroup.

13. The apparatus of claim 8 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising

identifying at least one node cluster in the graphical presentation of the covergroup to filter; and

selectively removing one or more nodes from the selected node cluster in the graphical presentation of the covergroup based, at least in part, on at least one of a coverage of the nodes, a cardinality associated with the nodes, or a distance between the coverpoints corresponding to the nodes.

14. The apparatus of claim 8 , wherein performing functional verification on the circuit design describing the electronic device further comprises:

generating test stimulus to provide to the electronic device modeled in a verification environment based on the circuit design; and

recording the coverpoints performed by the electronic device in response to the test stimulus.

15. A system comprising:

a memory system configured to store computer-executable instructions; and

a computing system, in response to execution of the computer-executable instructions, is configured to:

identify results of functional verification performed on a circuit design describing an electronic device;

determine occurrences of coverpoints within a covergroup based on the results of the functional verification of the circuit design, wherein each coverpoint corresponds to a signal state or a variable value in the circuit design during the functional verification; and

generate a graphical presentation of the covergroup, wherein the graphical presentation include nodes, at least a subset of which correspond to the coverpoints, and wherein the nodes are clustered in the graphical presentation based, at least in part, on the occurrences of the coverpoints during the functional verification of the circuit design.

16. The system of claim 15 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to determine occurrences of coverage crosses in the covergroup based, at least in part, on the results of the functional verification of the circuit design, and wherein each of the coverage crosses corresponds to a different plurality of the coverpoints occurring concurrently.

17. The system of claim 16 , wherein another subset of the nodes in the graphical presentation of the covergroup corresponds to the coverage crosses, and wherein the nodes are arranged in the graphical presentation of the covergroup based, at least in part, on a connectivity between the coverpoints and the coverage crosses.

18. The system of claim 15 , wherein generating the graphical presentation of the covergroup is performed by the computing system with a force-directed graph drawing algorithm.

19. The system of claim 15 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to

determine a rank of the coverpoints based, at least in part, on the occurrences of the coverpoints during the functional verification of the circuit design; and

annunciate the rank of one of the coverpoints in a corresponding node of the graphical presentation of the covergroup.

20. The system of claim 15 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to:

identify at least one node cluster in the graphical presentation of the covergroup to filter; and

selectively remove one or more nodes from the selected node cluster in the graphical presentation of the covergroup based, at least in part, on at least one of a coverage of the nodes, a cardinality associated with the nodes, or a distance between the coverpoints corresponding to the nodes.