Patent Assignment
Reel/Frame 056713/0076
Merger and Change of Name
Recorded: 2021-06-29
Pages: 7
Assignors
MENTOR GRAPHICS CORPORATION
Executed: 2020-12-30
SIEMENS INDUSTRY SOFTWARE INC.
Executed: 2020-12-30
Assignee
SIEMENS INDUSTRY SOFTWARE INC.
5800 GRANITE PARKWAY, SUITE 600, PLANO, TEXAS, 75024
Covered Properties
(78)
Interactive Loop Configuration in a Behavioral Synthesis Tool
Interactive Interface Resource Allocation in a Behavioral Synthesis Tool
Method and Apparatus for Selectively Compacting Test Responses
Continuous Application and Decompression of Test Patterns to a Circuit-Under-Test
Correlation of Behavioral Hdl Signals
Decompressor/Prpg for Applying Pseudo-Random and Deterministic Test Patterns
Structured Algorithmic Programming Language Approach to System Design
Reservation of Design Elements in a Parallel Printed Circuit Board Design Environment
Contrast Based Resolution Enhancement for Photolithographic Processing
Phase Shifter with Reduced Linear Dependency
Secure Exchange of Information in Electronic Design Automation
Automaton Synchronization During System Verification
Opc Simulation Model Using Socs Decomposition of Edge Fragments
Fragmentation Point and Simulation Site Adjustment for Resolution Enhancement Techniques
Matrix Optical Process Correction
Fault Diagnosis of Compressed Test Responses
Fault Dictionaries for Integrated Circuit Yield and Quality Analysis Methods and Systems
Power/Ground Wire Routing Correction and Optimization
Model-Based Sraf Insertion
Compactor Independent Direct Diagnosis of Test Hardware
Performing Memory Built-in-Self-Test (Mbist)
Synthesis Strategies Based on the Appropriate Use of Inductance Effects
Determining Mutual Inductance Between Intentional Inductors
Combined Host Interface Controller for Conducting Communication Between a Host System and Multiple Devices in Multiple Protocols
Calculation System for Inverse Masks
Extracting High Frequency Impedance in a Circuit Design Using an Electronic Design Automation Tool
Metastability Injector for a Circuit Description
Memory Re-Implementation for Field Programmable Gate Arrays
Conversion of Circuit Description to an Abstract Model of the Circuit
Flattening a Three-Dimensional Wire Harness Representation to Two Dimensions
Source Optimization for Image Fidelity and Throughput
Properties In Electronic Design Automation
Measure of Analysis Performed in Property Checking
Hierarchical Feature Extraction for Electrical Interaction Calculations
Removing the Effects of Unknown Test Values from Compacted Test Responses
Acyclic Modeling of Combinational Loops
Testing Embedded Memories in an Integrated Circuit
Direct Logic Diagnostics with Signature-Based Fault Dictionaries
Generating Test Patterns Having Enhanced Coverage of Untargeted Defects
Selectively Reducing the Number of Cell Evaluations in a Hardware Simulation
Generating Responses to Patterns Stimulating an Electronic Circuit with Timing Exception Paths
Automating Power Domains in Electronic Design Automation
Enhanced Diagnosis with Limited Failure Cycles
Opc Conflict Identification and Edge Priority System
Coherent State Among Multiple Simulation Models in an Eda Simulation Environment
Managing Communication Bandwidth in Co-Verification of Circuit Designs
Timing-Aware Test Generation and Fault Simulation
Integrated Circuit Layout Design Methodology with Process Variation Bands
Modelling and Simulation Method
Automating Interactions with Software User Interface
Patent:
10,698,702 →
Application:
15/666,355 →
Single Simulation-Based Structure Function Mapping
Dynamic Distributed Resource Management
Application:
15/873,827 →
Publication:
US 2019/0146847
Covergroup Network Analysis
Parasitic Extraction Using Topological Shape Descriptors
Thermal Model Obfuscation
Printed Circuit Board Thermal Conductivity Determination
Application:
16/105,411 →
Publication:
US 2019/0095563
Full Memory Logical Erase For Circuit Verification
Pixelized Thermal Conductivity Determination for Printed Circuit Boards
Cell-Aware Root Cause Deconvolution For Defect Diagnosis And Yield Analysis
Patent:
10,592,625 →
Application:
16/171,922 →
Selective Conditional Stall for Hardware-Based Circuit Design Verification
Patent:
10,579,776 →
Application:
16/174,382 →
Communication Protocols Design Verification Through Database Systems for Hardware-Based Emulation Platforms
Method And System For Cross-Tile OPC Consistency
Fault Campaign in Mixed Signal Environment
Input Data Compression For Machine Learning-Based Chain Diagnosis
Multi-Stage Machine Learning-Based Chain Diagnosis
Functional Safety Synthesis
Pattern-Based Optical Proximity Correction
Isometric Control Data Generation For Test Compression
Signal Probability-Based Test Cube Reordering And Merging
Machine Learning-Based Adjustments in Volume Diagnosis Procedures for Determination of Root Cause Distributions
Deep Learning Based Test Compression Analyzer
Application:
16/376,315 →
Publication:
US 2019/0311290
Automatic Moving Of Probe Locations For Parasitic Extraction
Fabric-Independent Multi-Patterning
Efficient Bi-Directional Property-Based Path Tracing
Layout Pattern Similarity Determination Based On Binary Turning Function Signatures
Machine Learning-Based Parasitic Extraction Automation for Circuit Design and Verification
System for Processing Messages of Data Stream
Scan Cell Architecture For Improving Test Coverage And Reducing Test Application Time
Related Assignments
(16)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 15, 2003
From: RAJSKI, JANUSZ; TYSZER, JERZY; KASSAB, MARK; MUKHERJEE, NILANJAN
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 014806/0270 →
Assignment of Assignor's Interest
Aug 3, 2004
From: RAJSKI, JANUSZ; TYSZER, JERZY; TAMARAPALLI, NAGESH
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015665/0129 →
Assignment of Assignor's Interest
Sep 30, 2004
From: KADKADE, SUDHIR DATTARAM; LYONS, CLIFTON ALTON, JR.
To: LIGHTHOUSE DESIGN AUTOMATION, INC.
Reel/Frame 015868/0565 →
Assignment of Assignor's Interest
Oct 12, 2004
From: FERGUSON, JOHN G.; PIKUS, FEDOR G.; SAKAJIRI, KYOHEI; GRODD, LAURENCE W.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015238/0864 →
Assignment of Assignor's Interest
Nov 4, 2004
From: ROBLES, JUAN ANDRES TORRES; GRANIK, YURI
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015343/0736 →
Assignment of Assignor's Interest
Nov 4, 2004
From: PETUNIN, VLADIMIR V.; PFEIL, CHARLES L.; POTTS, HENRY; SHIKALOV, VLADIMIR B.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015965/0155 →
Assignment of Assignor's Interest
May 17, 2005
From: ADAM, KONSTANTINOS
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016023/0958 →
Assignment of Assignor's Interest
Aug 24, 2005
From: WORD, JAMES; COBB, NICOLAS B.; LACOUR, PATRICK J.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016443/0174 →
Assignment of Assignor's Interest
Oct 24, 2005
From: RAJSKI, JANUSZ; CHEN, GANG; KEIM, MARTIN; TAMARAPALLI, NAGESH
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016675/0106 →
Assignment of Assignor's Interest
Nov 22, 2005
From: RAJSKI, JANUSZ; MRUGALSKI, GRZEGORZ; POGIEL, ARTUR; TYSZER, JERZY
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016809/0189 →
Assignment of Assignor's Interest
Jul 13, 2006
From: LIGHTHOUSE DESIGN AUTOMATION, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 017929/0304 →
Assignment of Assignor's Interest
Nov 17, 2006
From: WATERS, SIMON JOSHUA; GUTBERLET, PETER PIUS; TAKACH, ANDRES R.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 018554/0222 →
Assignment of Assignor's Interest
Apr 7, 2008
From: SPEEDGATE, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 020762/0784 →
Assignment of Assignor's Interest
Dec 21, 2011
From: MENTOR GRAPHICS CORPORATION
To: CALYPTO DESIGN SYSTEMS, INC.
Reel/Frame 027428/0867 →
Assignment of Assignor's Interest
Dec 13, 2018
From: CALYPTO DESIGN SYSTEMS, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 047766/0077 →
Assignment of Assignor's Interest
Jan 24, 2019
From: GRANIK, YURI; COBB, NICOLAS
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 048121/0651 →