Input data compression for machine learning-based chain diagnosis
Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.
1. A method, executed by at least one processor of a computer, comprising:
receiving a circuit design and test patterns for testing circuits manufactured based on the circuit design;
preparing training samples based on the circuit design and the test patterns, comprising:
injecting faults into scan chains in the circuit design,
performing simulations on the fault-injected circuit design to determine test response patterns in response to the test patterns, the test response patterns being captured by the scan chains,
determining unloaded test response patterns, the unloaded test response patterns being patterns obtained by shifting the test response patterns out of the scan chains,
determining observed failing bit patterns based on comparing the unloaded test response patterns with corresponding good-machine test response patterns, and
performing bit-reduction on the observed failing bit patterns for each of the fault injections to construct the training samples, the bit-reduction comprising pattern-based bit compression or cycle-based bit compression for each of the scan chains;
training machine-learning models for faulty scan cell identification using the training samples; and
storing the trained machine-learning models.
2. The method recited in claim 1 , further comprising:
using the trained machine-learning models to identify defective scan cell candidates for circuits having failed manufacture tests; and
locating defects in one or more of the circuits having failed manufacture tests based on the defective scan cell candidates.
3. The method recited in claim 2 , wherein the locating comprises:
using a physical failure analysis tool to analyze the one or more of the circuits having failed manufacture tests.
4. The method recited in claim 1 , wherein the bit-reduction further comprises bit filtering.
5. The method recited in claim 4 , wherein the bit filtering comprises:
removing bits of the compressed observed failing bit patterns that are associated with scan cells that have no logic path to any scan cells on a faulty scan chain from the training samples construction.
6. The method recited in claim 4 , wherein the bit filtering comprises:
removing bits that never fail for any of the test patterns or for any of the fault injections into a faulty scan chain from the training samples construction.
7. The method recited in claim 4 , wherein the bit filtering comprises:
keeping only sensitive bits on faulty scan chains for the training samples construction, the faulty scan chains being scan chains with the faults being injected into.
8. The method recited in claim 1 , wherein the combining in the pattern-based bit compression and in the cycle-based bit compression comprises:
performing bit addition, wherein the observed failing bit patterns use “1” and “0” to represent a failing bit and a non-failing bit, respectively.
9. The method recited in claim 1 , wherein the combining in the pattern-based bit compression and in the cycle-based bit compression comprises:
computing observed bit failing probability values based on the observed failing bit patterns.
10. The method recited in claim 1 , wherein the machine-learning models are Artificial Neural Networks.
11. The method recited in claim 1 , wherein the faults are represented by fault types and fault probabilities.
12. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
receiving a circuit design and test patterns for testing circuits manufactured based on the circuit design;
preparing training samples based on the circuit design and the test patterns, comprising:
injecting faults into scan chains in the circuit design,
performing simulations on the fault-injected circuit design to determine test response patterns in response to the test patterns, the test response patterns being captured by the scan chains,
determining unloaded test response patterns, the unloaded test response patterns being patterns obtained by shifting the test response patterns out of the scan chains,
determining observed failing bit patterns based on comparing the unloaded test response patterns with corresponding good-machine test response patterns, and
performing bit-reduction on the observed failing bit patterns for each of the fault injections to construct training samples, the bit-reduction comprising pattern-based bit compression or cycle-based bit compression for each of the scan chains
training machine-learning models for faulty scan cell identification using the training samples; and
storing the trained machine-learning models.
13. The one or more non-transitory computer-readable media recited in claim 12 , wherein the method further comprises:
using the trained machine-learning models to identify defective scan cell candidates for circuits having failed manufacture tests.
14. The one or more non-transitory computer-readable media recited in claim 13 , wherein the bit-reduction further comprises bit filtering.
15. The one or more non-transitory computer-readable media recited in claim 14 , wherein the bit filtering comprises:
removing bits of the compressed observed failing bit patterns that are associated with scan cells that have no logic path to any scan cells on a faulty scan chain from the training samples construction.
16. The one or more non-transitory computer-readable media recited in claim 14 , wherein the bit filtering comprises:
removing bits that never fail for any of the test patterns or for any of the fault injections into a faulty scan chain from the training samples construction.
17. The one or more non-transitory computer-readable media recited in claim 14 , wherein the bit filtering comprises:
keeping only sensitive bits on faulty scan chains for the training samples construction, the faulty scan chains being scan chains with the faults being injected into.
18. The one or more non-transitory computer-readable media recited in claim 12 , wherein the combining in the pattern-based bit compression and in the cycle-based bit compression comprises:
performing bit addition, wherein the observed failing bit patterns use “1” and “0” to represent a failing bit and a non-failing bit, respectively.
19. The one or more non-transitory computer-readable media recited in claim 12 , wherein the combining in the pattern-based bit compression and in the cycle-based bit compression comprises:
computing observed bit failing probability values based on the observed failing bit patterns.
20. The one or more non-transitory computer-readable media recited in claim 12 , wherein the machine-learning models are Artificial Neural Networks.
21. The one or more non-transitory computer-readable media recited in claim 12 , wherein the faults are represented by fault types and fault probabilities.