Efficient bi-directional property-based path tracing
Systems and methods for efficient bi-directional property-based path tracing. The method includes reading a data structure corresponding to a circuit. The method also includes iteratively performing property accounting of properties as voltages propagate across devices in the circuit. The method also includes traversing series chains of similar devices in the circuit to reduce an iteration count and arrive at a circuit stability, wherein the circuit stability is determined when propagated user-specified and computed circuit properties (e.g. shortest distance) remain unchanged between subsequent iterations of the traversing. The method also includes traversing the data structure for propagated user-specified and computed property violations. The method also includes cataloging and reporting these violations in human-readable form.
1. A method for efficient bi-directional property-based path tracing, comprising:
reading a data structure corresponding to a circuit;
traversing series chains of similar devices in the circuit to reduce an iteration count and arrive at a circuit stability, wherein the circuit stability is determined when propagated user-specified and computed circuit properties remain unchanged between subsequent iterations of the traversing;
iteratively performing property accounting of properties as voltages propagate across devices in the circuit;
traversing the data structure for the propagated user-specified and computed property violations; and
cataloging and reporting the propagated user-specified and computed violations in human-readable form.
2. The method of claim 1 , further comprising:
recognizing a series chain in the circuit, which includes:
ordering the similar devices in a manner that an iteration-to-property-stability count is a constant value; and
storing property information with device information in the data structure.
3. The method of claim 2 , further comprising:
interrogating pin voltages and corresponding properties on each pin of the devices; and
storing the pin voltages and the corresponding properties with the device information in the data structure.
4. The method of claim 1 , further comprising:
traversing the circuit backwards from a user-specified start point to a voltage source to construct a propagated net-pin-device-pin-net-pin-device circuit path.
5. The method of claim 1 , wherein:
a number of iterations required to attain propagated property stability is reduced by recognizing hierarchical elements and repetitive elements in the circuit,
the hierarchical elements are identified explicitly in the read data structure or recognized during the iteratively performed property accounting of the properties, and
the repetitive elements are identified by pattern-matching and topological analysis in the iteratively performed property accounting of the properties.
6. The method of claim 1 , wherein the iteratively performed property accounting of the properties includes:
prioritizing device iteration direction of current flow to reduce an iteration-to-property-stability count using circuit theory laws.
7. The method of claim 1 , wherein:
when a property stability of a propagated user-specified property is conditional on a second property, circuit stability is attained when both the user-specified property and the second propagated property remain unchanged for all devices and nets between subsequent iterations.
8. A computer system comprising:
a processor; and
an accessible memory, the computer system configured to:
read a data structure corresponding to a circuit;
traverse series chains of similar devices in the circuit to reduce an iteration count and arrive at a circuit stability, wherein the circuit stability is determined when propagated user-specified circuit properties remain unchanged between subsequent iterations of the traversing;
iteratively perform property accounting of properties as voltages propagate across devices in the circuit;
traverse the data structure for propagated user-specified and computed property violations; and
catalog and report the propagated user-specified and computed property violations in human-readable form.
9. The computer system of claim 8 is further configured to perform:
recognizing a series chain in the circuit, which includes:
ordering the similar devices in a manner that an iteration-to-property-stability count is a constant value; and
storing property information with device information in the data structure.
10. The computer system of claim 9 is further configured to perform:
interrogating pin voltages and corresponding properties on each pin of the devices; and
storing the pin voltages and the corresponding properties with the device information in the data structure.
11. The computer system of claim 8 is further configured to perform:
traversing the circuit backwards from a user-specified start point to a voltage source to construct a propagated net-pin-device-pin-net-pin-device circuit path.
12. The computer system of claim 8 , wherein:
a number of iterations required to attain propagated property stability is reduced by recognizing hierarchical elements and repetitive elements in the circuit,
the hierarchical elements are identified explicitly in the read data structure or recognized during the iteratively performed property accounting of the properties, and
the repetitive elements are identified by pattern-matching and topological analysis in the iteratively performed property accounting of the properties.
13. The computer system of claim 8 , wherein the iteratively performed property accounting of the properties includes:
prioritizing device iteration direction of current flow to reduce an iteration-to-property-stability count using circuit theory laws.
14. The computer system of claim 8 , wherein:
when a property stability of a propagated user-specified property is conditional on a second property, circuit stability is attained when both the user-specified property and the second propagated property remain unchanged for all devices and nets between subsequent iterations.
15. A non-transitory computer-readable medium storing with executable instructions that, when executed, cause one or more computer systems to:
read a data structure corresponding to a circuit;
traverse series chains of similar devices in the circuit to reduce an iteration count and arrive at a circuit stability, wherein the circuit stability is determined when propagated user-specified circuit properties remain unchanged between subsequent iterations of the traversing;
iteratively perform property accounting of properties as voltages propagate across devices in the circuit;
traverse the data structure for propagated user-specified and computed property violations; and
catalog and report these violations in human-readable form.
16. The non-transitory computer-readable medium of claim 15 , wherein the executable instructions that, when executed, further cause the one or more computer system to perform:
recognizing a series chain in the circuit, which includes:
ordering the similar devices in a manner that an iteration-to-property-stability count is a constant value; and
storing property information with device information in the data structure.
17. The non-transitory computer-readable medium of claim 16 , wherein the executable instructions that, when executed, further cause the one or more computer system to perform:
interrogating pin voltages and corresponding properties on each pin of the devices and nets; and
storing the pin voltages and the corresponding properties with the device and net information in the data structure.
18. The non-transitory computer-readable medium of claim 15 , wherein the executable instructions that, when executed, further cause the one or more computer system to perform:
traversing the circuit backwards from a user-specified start point to a voltage source to construct a propagated net-pin-device-pin-net-pin-device circuit path.
19. The non-transitory computer-readable medium of claim 15 , wherein:
a number of iterations required to attain property stability is reduced by recognizing hierarchical elements and repetitive elements in the circuit,
the hierarchical elements are identified explicitly in the read data structure or recognized during the iteratively performed property accounting of the properties, and
the repetitive elements are identified by pattern-matching and topological analysis in the iteratively performed property accounting of the properties.
20. The non-transitory computer-readable medium of claim 15 , wherein the iteratively performed property accounting of the properties includes:
prioritizing device iteration direction of current flow to reduce an iteration-to-property-stability count using circuit theory laws.
21. The non-transitory computer-readable medium of claim 15 , wherein:
when a property stability of a propagated user-specified property is conditional on a second property, circuit stability is attained when both the user-specified property and the second propagated property remain unchanged for all devices and nets between subsequent iterations.