Multiport memory, memory macro and semiconductor device

1. A circuit comprising:

a memory cell array which includes:

a plurality of memory cells;

a plurality of word lines coupled to the memory cells, respectively, and

a plurality of bit lines coupled to the memory cells,

an address control circuit which includes:

a first latch circuit into which a first address signal is input and from which a first output signal is output;

a selection circuit into which a second address signal and the first output signal are input and which selects the first output signal or the second address signal for outputting the first output signal or the second address signal as a second output signal;

a second latch circuit into which the second output signal is input and from which a third output signal is output;

a decode circuit which decodes the third output signal and outputs a fourth output signal; and

a word line drive circuit which drives and thereby activates one of the word lines selected based on the fourth output signal for reading data stored in one of the memory cells or for writing data to one of the memory cells,

wherein the word line drive circuit drives the selected one of the word lines at a timing which is based on a word line control signal, and

wherein the second latch circuit latches the second output signal at the timing which is based on the word line control signal.

2. The circuit according to claim 1 , further comprising:

a control circuit generating the word line control signal to drive the selected one of the word lines two times per one period of a clock signal from the clock signal.

3. The circuit according to claim 2 ,

wherein the control circuit includes a pulse generation circuit, a reset-set latch circuit, first and second delay circuits and a logic circuit,

wherein the pulse generation circuit generates a one-shot pulse signal in response to a transition of rising or falling of the clock signal,

wherein the reset-set latch circuit generates a first pulse signal which is set with the one-shot pulse signal and is reset with a feedback signal,

wherein the first delay circuit generates the feedback signal by delaying the first pulse signal,

wherein the second delay circuit generates a second pulse signal by delaying the first pulse signal which has been delayed by the first delay circuit, and

wherein the logic circuit generates the word line control signal from the first pulse signal and the second pulse signal.

4. The circuit according to claim 2 ,

wherein the control circuit includes a pulse generation circuit, a reset-set latch circuit, first and second delay circuits and first and second logic circuits,

wherein the pulse generation circuit generates a one-shot pulse signal in response to a transition of rising or falling of the clock signal,

wherein the reset-set latch circuit generates a third pulse signal which is set with the one-shot pulse signal and is reset with a feedback signal,

wherein the first logic circuit generates a first pulse signal from the one-shot pulse signal and the third pulse signal,

wherein the first delay circuit generates the feedback signal by delaying the first pulse signal,

wherein the second delay circuit generates a second pulse signal by delaying the first pulse signal which has been delayed by the first delay circuit, and

wherein the second logic circuit generates the word line control signal from the first pulse signal and the second pulse signal.

5. The circuit according to claim 1 ,

wherein the address control circuit is set as a first address control circuit, the decode circuit is set as a first decode circuit, the word line drive circuit is set as a first word line drive circuit, the clock signal is set as a first clock signal, the word line is set as a first word line, and the memory cell array further includes a plurality of second word lines in addition to a plurality of the first word lines,

wherein the circuit further comprises a second address control circuit and a second clock signal and a third address signal are further input into the circuit, and

wherein the second address control circuit includes a third latch circuit which latches the third address signal in synchronization with the second clock signal, a second decode circuit which decodes the third address signal which has been latched by the third latch circuit, and a second word line drive circuit which selects and drives one of the second word lines that the memory cell array includes on the basis of an output signal from the second decode circuit.

6. The circuit according to claim 2 , further comprising:

a read/write amplifier coupled to the bit lines; and

an input-output data buffer coupled to the read/write amplifier.

7. The circuit according to claim 6 ,

wherein the first address signal is input from a first address port into the first latch circuit,

wherein the second address signal is input from a second address port into the second latch circuit, and

wherein the first address port is separated from the second address port.

8. The circuit according to claim 7 ,

wherein the input-output data buffer is coupled to a first data port for inputting data to the memory cell array and a second data port for outputting data from the memory cell array.