FinFET devices and methods of forming

1. A device comprising:

a first n-type transistor comprising:

a first fin, the first fin comprising a first material on a first dielectric material on a substrate,

a first epitaxial source/drain region and a second epitaxial source/drain region each in a respective first recess in the first fin, the first fin being disposed between the first epitaxial source/drain region and the second epitaxial source/drain region, and

a first gate stack on the first fin; and

a second n-type transistor comprising:

a second fin, the second fin comprising a second material on the substrate,

a third epitaxial source/drain region and a fourth epitaxial source/drain region each in a respective second recess in the second fin, the second fin being disposed between the third epitaxial source/drain region and the fourth epitaxial source/drain region, and

a second gate stack on the second fin.

2. The device of claim 1 , wherein the first material and the second material are a same material.

3. The device of claim 1 , wherein the first material and the second material are both silicon.

4. The device of claim 1 , wherein a depth of the second recess is greater than a depth of the first recess.

5. The device of claim 1 , wherein a width of each respective second recess at a top surface of the second fin is greater than a width of each respective first recess at a top surface of the first fin.

6. The device of claim 1 , wherein the first n-type transistor is in a core logic region of the substrate, and the second n-type transistor is in an input/output region of the substrate.

7. The device of claim 1 , wherein each of the first epitaxial source/drain region and the second epitaxial source/drain region do not completely fill the respective first recesses, and wherein each of the third epitaxial source/drain region and the fourth epitaxial source/drain region at least completely fill the respective second recesses.

8. The device of claim 1 , wherein each of the first epitaxial source/drain region and the second epitaxial source/drain region has a first proximity distance, the first proximity distance being between a nearest surface of the respective first epitaxial source/drain region and the second epitaxial source/drain region to the first gate stack and a plane of a respective nearest sidewall of the first gate stack, and wherein each of the third epitaxial source/drain region and the fourth epitaxial source/drain region has a second proximity distance, the second proximity distance being between a nearest surface of the respective third epitaxial source/drain region and the fourth epitaxial source/drain region to the second gate stack and a plane of a respective nearest sidewall of the second gate stack, the first proximity distance being the same as the second proximity distance.

9. The device of claim 1 further comprising:

a first p-type transistor comprising:

a third fin, the third fin comprising a third material on the substrate,

a fifth epitaxial source/drain region and a sixth epitaxial source/drain region each in a respective third recess in the third material, the third material being a different material from the second material, the third fin being disposed between the first epitaxial source/drain region and the second epitaxial source/drain region, and

a third gate stack on the third fin; and

a second p-type transistor comprising:

a fourth fin, the fourth fin comprising a fourth material on the substrate, the fourth material being a different material from the third material,

a seventh epitaxial source/drain region and a eighth epitaxial source/drain region each in a respective fourth recess in the fourth material, the fourth fin being disposed between the seventh epitaxial source/drain region and the eighth epitaxial source/drain region, and

a fourth gate stack on the fourth fin.

10. The device of claim 9 , wherein the fourth material is a same a material as the second material.

11. The device of claim 9 , wherein a depth of the third recess is greater than a depth of the fourth recess.

12. The device of claim 9 , wherein a width of each respective fourth recess at a top surface of the fourth fin is greater than a width of each respective third recess at a top surface of the third fin.

13. A method comprising:

forming a first fin on a substrate, the first fin comprising a first crystalline material on the substrate;

forming a second fin on the substrate, the second fin comprising a second crystalline material on the substrate, a material of the first crystalline material being different from a material of the second crystalline material;

forming a first structure on the first crystalline material of the first fin and a second structure on the second crystalline material of the second fin;

forming a first spacer along a sidewall of the first structure and a second spacer along a sidewall of the second structure;

simultaneously etching the first crystalline material and the second crystalline material to form a first recess in the first fin and adjacent the first spacer, and a second recess in the second fin and adjacent the second spacer, a width of the first recess at a top surface of the first fin is less than a width of the second recess at a top surface of the second fin, a depth of the first recess is greater than a depth of the second recess; and

epitaxially growing a first epitaxial source/drain region in the first recess and a second source/drain region in the second recess.

14. The method of claim 13 , wherein the first recess extends laterally under the first spacer further than the second recess laterally extends under the second spacer.

15. The method of claim 13 , wherein the first crystalline material is silicon-germanium, and the second crystalline material is silicon.

16. The method of claim 13 , wherein the simultaneously etching includes etching the first crystalline material at a first vertical etching rate and etching the second crystalline material at a second vertical etching rate, the first vertical etching rate being greater than the second vertical etching rate.

17. The method of claim 13 , wherein the simultaneously etching includes etching the first crystalline material at a first lateral etching rate and etching the second crystalline material at a second lateral etching rate, the first lateral etching rate being greater than the second lateral etching rate.

18. A method comprising:

forming a first fin in an n-type core logic region of a substrate, the first fin comprising a first crystalline material and a dielectric material, the dielectric material being on the substrate, the first crystalline material being on the dielectric material;

forming a second fin in an n-type input/output (I/O) region of the substrate, the second fin comprising a second crystalline material on the substrate, materials of the first crystalline material and the second crystalline material a same material;

forming a first gate structure on the first fin and a second gate structure on the second fin;

forming a first spacer along a sidewall of the first gate structure and a second spacer along a sidewall of the second gate structure;

simultaneously etching the first fin to form a first recess in the first fin and a second recess in the second fin, the first recess being adjacent the first spacer and the second recess being adjacent the second spacer, the second recess having a greater depth than the first recess, the first recess and the second recess extending laterally a same distance under the first spacer and the second spacer, respectively; and

epitaxially growing a first source/drain region in the first recess and a second source/drain region in the second recess.

19. The method of claim 18 , wherein the second crystalline material is etched at a greater vertical etching rate than the first crystalline material, and the second crystalline material is etched at a same lateral etching rate as the first crystalline material.

20. The method of claim 18 , wherein the first crystalline material and the second crystalline material are silicon.