Vertical FET with strained channel

1. A method for forming a semiconductor structure, the method comprising:

depositing a strain relaxed buffer (SRB) layer over a substrate;

recessing the SRB layer on a first region of the structure;

forming a first semiconductor layer on the first region of the structure;

depositing one or more mandrels over the first semiconductor layer of the first region of the structure;

depositing a spacer layer over the one or more mandrels, the spacer layer comprising vertical portions and horizontal portions;

removing the one or more mandrels and the horizontal portions of the spacer layer; and

removing material unprotected by the spacer to form a first channel for a p-type vertical field effect transistor from the first semiconductor layer, wherein the first channel includes a compressive strain.

2. The method of claim 1 , wherein:

the semiconductor structure is a complementary semiconductor; and

the method further comprises:

depositing one or more mandrels over the SRB layer of a second region of the structure;

patterning one or more fins of SRB layer in the second region of the structure, using the one or more mandrels as a mask; and

epitaxially growing a second semiconductor layer on the exposed sidewalls of the one or more fins;

wherein performing a reactive ion etch to remove material unprotected by the spacer form a second channel for an n-type vertical field effect transistor from the second semiconductor layer;

wherein the second channel is unstrained.

3. The method of claim 2 further comprising placing a block mask on the second region to prevent formation of the first semiconductor layer on the second region.

4. The method of claim 3 further comprising filling a region between gaps between the second semiconductor layer on the exposed sidewalls of the one or more fins with amorphous silicon.

5. The method of claim 2 , wherein the second semiconductor layer comprises silicon.

6. The method of claim 1 , wherein the first semiconductor layer comprises silicon.

7. The method of claim 1 , wherein:

the substrate comprises silicon; and

the SRB layer comprises silicon germanium.

8. The method of claim 1 , wherein the mandrel comprises a nitride.

9. The method of claim 1 , wherein the mandrel comprises an oxide.

10. The method of claim 1 , wherein the spacer layer comprises a dielectric material.

11. A semiconductor structure, comprising:

a substrate:

a strain relaxed buffer (SRB) layer over the substrate;

a first channel for a p-type vertical field effect transistor; wherein the first channel includes a compressive strain; and

a second channel for an n-type vertical field effect transistor; wherein the second channel is unstrained;

wherein the first channel is formed by a method comprising:

depositing a first semiconductor layer over the SRB layer in a first region of the structure;

depositing a first mandrel over the first semiconductor layer;

depositing a spacer layer over the first mandrel, the spacer layer comprising vertical portions and horizontal portions;

removing the first mandrel and the horizontal portions of the spacer layer; and

performing a reactive ion etch to remove material unprotected by remaining portions of the spacer layer to form the first channel from the first semiconductor layer;

wherein the second channel is formed by a method comprising:

depositing a second mandrel over the SRB layer in a second region of the structure;

patterning one or more fins from the SRB layer in the second region of the structure, using the second mandrel as a mask;

epitaxially growing a second semiconductor layer on sidewalls of the one or more fins;

depositing the spacer layer over the second mandrel; and

performing a reactive ion etch to remove material unprotected by the spacer layer to form the second channel from the second semiconductor layer.

12. The semiconductor structure of claim 11 , wherein the method further comprises

placing a block mask on the second region to prevent formation of the first semiconductor layer on the second region.

13. The semiconductor structure of claim 12 , further comprising filling a region between gaps between the second semiconductor layer on the exposed sidewalls of the one or more fins with amorphous silicon.

14. The semiconductor structure of claim 11 , wherein the second semiconductor layer comprises silicon.

15. The semiconductor structure of claim 11 , wherein the first semiconductor layer comprises silicon.

16. The semiconductor structure of claim 11 , wherein:

the substrate comprises silicon; and

the SRB layer comprises silicon germanium.

17. A method for forming a complementary semiconductor structure, the method comprising:

depositing a strain relaxed buffer (SRB) layer over a substrate;

recessing the SRB layer on a first region of the structure;

forming a first semiconductor layer on the first region of the structure;

depositing one or more mandrels over the first semiconductor layer of the first region of the structure;

depositing a spacer layer over the one or more mandrels, the spacer layer comprising vertical portions and horizontal portions;

removing the one or more mandrels and the horizontal portions of the spacer layer;

removing material unprotected by the spacer to form a first channel for a p-type vertical field effect transistor from the first semiconductor layer;

depositing one or more mandrels over the SRB layer of a second region of the structure;

patterning one or more fins of SRB layer in the second region of the structure, using the one or more mandrels as a mask;

epitaxially growing a second semiconductor layer on the exposed sidewalls of the one or more fins; and

removing material unprotected by the spacer to form a second channel for an n-type vertical field effect transistor from the second semiconductor layer; wherein

the first channel has a compressive strain; and

the second channel is unstrained.

18. The method of claim 17 , further comprising:

placing a block mask on the second region to prevent formation of the first semiconductor layer on the second region; and

filling a region between gaps between the second semiconductor layer on the exposed sidewalls of the one or more fins with amorphous silicon.

19. The method of claim 17 , wherein:

the first semiconductor layer comprises silicon;

the second semiconductor layer comprises silicon.