In-layer Signal processing

1. An electronic display assembly comprising:

a circuit board;

a sensor array located on one side of the circuit board, the sensor array comprising at least a first and a second sensor pixel unit, each of the first and second sensor pixel units comprising a plurality of sensor pixels;

an electronic display array located on an opposite side of the circuit board from the sensor array, the electronic display array comprising at least a first and a second display pixel unit, each of the first and second display pixel units comprising a plurality of display pixels; and

a logic unit layer coupled to one side of the circuit board, the logic unit layer comprising at least a first and a second logic unit, wherein:

the first logic unit is operable to:

receive first sensor signals from the first sensor pixel unit, the first sensor signals communicated using a particular signal protocol, the first sensor signals corresponding to light captured by the plurality of sensor pixels of the first sensor pixel unit;

perform at least one operation on the received first sensor signals to create first display signals; and

transmit the first display signals to the first display pixel unit, the first display signals communicated using the particular signal protocol, the first display signals operable to instruct the first display pixel unit to display light corresponding to the light captured by the plurality of sensor pixels of the first sensor pixel unit; and

the second logic unit is operable to:

receive second sensor signals from the second sensor pixel unit, the second sensor signals communicated using the particular signal protocol, the second sensor signals corresponding to light captured by the plurality of sensor pixels of the second sensor pixel unit;

perform at least one operation on the received second sensor signals to create second display signals; and

transmit the second display signals to the second display pixel unit, the second display signals communicated using the particular signal protocol, the second display signals operable to instruct the second display pixel unit to display light corresponding to the light captured by the plurality of sensor pixels of the second sensor pixel unit.

2. The electronic display assembly of claim 1 , wherein the logic unit layer is between the sensor array and the circuit board.

3. The electronic display assembly of claim 2 , wherein the logic unit layer and the sensor array are combined into a single three-dimensional integrated circuit using through-silicon vias.

4. The electronic display assembly of claim 1 , wherein the logic unit layer is between the electronic display array and the circuit board.

5. The electronic display assembly of claim 4 , wherein the logic unit layer and the electronic display array are combined into a single three-dimensional integrated circuit using through-silicon vias.

6. The electronic display assembly of claim 1 , wherein:

the particular signal protocol comprises a chip-to-chip interconnect protocol; and

performing the at least one operation on the received first and second sensor signals comprises transforming the received first and second sensor signals to include augmented information for display on the first and second display pixel units.

7. The electronic display assembly of claim 6 , wherein the chip-to-chip interconnect protocol comprises low-voltage differential signaling (LVDS) or Inter-Integrated Circuit (I 2 C).

8. An electronic display assembly comprising:

a sensor array located on one side of a circuit board, the sensor array comprising one or more sensor pixel units, each sensor pixel unit comprising a plurality of sensor pixels;

an electronic display array located on an opposite side of the circuit board from the sensor array, the electronic display array comprising one or more display pixel units, each display pixel unit comprising a plurality of display pixels; and

a logic unit layer coupled to one side of the circuit board, the logic unit layer comprising a plurality of logic units, the logic unit layer configured to:

receive first signals from the sensor array, the first signals communicated using a particular signal protocol, the first signals corresponding to light captured by the plurality of sensor pixels;

perform at least one operation on the received first signals to create second signals; and

transmit the second signals to the electronic display array, the second signals communicated using the particular signal protocol of the first signals, the second signals operable to instruct the electronic display array to display light corresponding to the light captured by the plurality of sensor pixels.

9. The electronic display assembly of claim 8 , wherein the logic unit layer is between the sensor array and the circuit board.

10. The electronic display assembly of claim 9 , wherein the logic unit layer and the sensor array are combined into a single three-dimensional integrated circuit using through-silicon vias.

11. The electronic display assembly of claim 8 , wherein the logic unit layer is between the electronic display array and the circuit board.

12. The electronic display assembly of claim 11 , wherein the logic unit layer and the electronic display array are combined into a single three-dimensional integrated circuit using through-silicon vias.

13. The electronic display assembly of claim 8 , wherein:

the particular signal protocol comprises a chip-to-chip interconnect protocol; and

performing the at least one operation on the received first signals to create second signals comprises transforming the received first signals to include augmented information for display on the electronic display array.

14. The electronic display assembly of claim 13 , wherein the chip-to-chip interconnect protocol comprises low-voltage differential signaling (LVDS) or Inter-Integrated Circuit (I 2 C).