Issuing instructions to multiple execution units
A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
1. A processor comprising:
a field of execution units arranged in at least a two-dimensional pattern, wherein the execution units receive a plurality of data words from a memory for processing, wherein an operation of each respective execution unit of the field of execution units is controlled by a respective instruction issued to the respective execution unit, the plurality of data words including the respective instruction,
the processor having at least one operation mode in which one or more of the instructions remain valid for multiple clock cycles of the processor, wherein multiple data words of the plurality of data words are processed by the respective execution units during the multiple clock cycles,
wherein result data produced by a first set of execution units of the field of execution units are transmitted via an interconnect structure to at least one execution unit of a second set of execution units of the field of execution units, and
wherein, in the at least one operation mode, data transmission to and from the field of execution units is monitored and synchronized with the field of execution units outside the field of execution units by one or more synchronization units in communication with the field of execution units, and data processing in the field of execution units is performed such that no synchronization of the data processing is required between execution units inside the field of execution units.
2. The processor according to claim 1 , wherein the one or more synchronization units include:
a state machine, wherein in response to data not being available to the field of execution units, the state machine is configured to generate wait states for the field of execution units, and
first-in-first-out units (FIFOs) associated with the field of execution units, wherein in response to the data becoming available to the field of execution units, the FIFOs use one of valid flags or availability level indicators to signal the availability of the data to the state machine.
3. The processor according to claim 1 , wherein the field of execution units processes the data words as a capsule in response to all capsule-interfacing components of the processor being ready, wherein the capsule-interfacing components are configured to communicate data transfers with the capsule and are outside the field of execution units, and wherein the operation inside the capsule is solely controlled by flags indicating the validity of data transferred to inside the capsule.
4. The method according to claim 3 , wherein all of the capsule-interfacing components are ready if all source components of the capsule-interfacing components are able to provide data to the capsule and data output by the capsule is acceptable by all receiving components of the capsule-interfacing components.
5. The method according to claim 4 , wherein the capsule includes the field of execution units and a state machine and FIFOs are provided externally to the capsule to synchronize data transmission to and from the field of execution units.
6. A method comprising:
receiving a plurality of data words at a field of execution units of a processor from a memory for processing, wherein the field of execution units are arranged in at least a two-dimensional pattern;
performing data processing in the field of execution units such that no synchronization of the data processing is required between execution units inside the field of execution units, wherein an operation of each respective execution unit of the field of execution units is controlled by a respective instruction issued to the respective execution unit, the plurality of data words including the respective instruction,
wherein one or more of the instructions remain valid for multiple clock cycles of the processor, wherein multiple data words of the plurality of data words are processed by the respective execution units during the multiple clock cycles,
wherein performing the data processing includes transmitting result data produced by a first set of execution units of the field of execution units via an interconnect structure to at least one execution unit of a second set of execution units of the field of execution units; and
monitoring and synchronizing data transmission to and from the field of execution units outside the field of execution units by one or more synchronization units in communication with the field of execution units.
7. The method according to claim 6 , wherein monitoring and synchronizing the data transmission includes:
in response to data not being available to the field of execution units, generating wait states for the field of execution units using a state machine of the one or more synchronization units; and
in response to the data becoming available to the field of execution units, using one of valid flags or availability level indicators to signal the availability of the data to the state machine by first-in-first-out units (FIFOs) of the one or more synchronization units, wherein the FIFOs are associated with the field of execution units.
8. The method according to claim 7 , further comprising triggering one of an interrupt, a processor exception, or a trap in the processor after a particular amount of clock cycles has passed without the data becoming available to the field of execution units.
9. The method according to claim 6 , wherein performing the data processing is performed in a capsule, and is performed in response to all capsule-interfacing components of the processor being ready, wherein the capsule-interfacing components are configured to communicate data transfers with the capsule and are outside the field of execution units, and wherein the data processing inside the capsule is solely controlled by flags indicating the validity of data transferred to inside the capsule.
10. The method according to claim 9 , wherein all of the capsule-interfacing components are ready if all source components of the capsule-interfacing components are able to provide data to the capsule and data output by the capsule is acceptable by all receiving components of the capsule-interfacing components.