Fan-out semiconductor package
A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip disposed in the through hole and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filling at least a portion of the through hole, and a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad.
1. A semiconductor package comprising:
a core member having a first through hole, and including a first insulating layer having a second through hole and a third through hole:
a first dummy structure disposed in the second through hole of the first insulating layer of the core member;
a second dummy structure disposed in the third through hole of the first insulating layer of the core member;
a semiconductor chip disposed in the first through hole, and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface;
an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filling at least a portion of the first through hole; and
a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad,
wherein the first dummy structure is electrically insulated from the semiconductor chip,
the core member further including a third insulating layer penetrated by the first through hole, and
the third insulating layer covers at least a portion of the first insulating layer and fills at least a portion of the second through hole of the first insulating layer of the core member, and having a portion covering the first dummy structure to separate the first dummy structure from the encapsulant,
wherein the first dummy structure is electrically insulated from the redistribution layer of the connection member, and
an arrangement of the semiconductor chip, the first dummy structure and the second dummy structure is configured to reduce a package-level warpage.
2. The semiconductor package of claim 1 , wherein the first dummy structure comprises silicon.
3. The semiconductor package of claim 2 , wherein the first dummy structure is a silicon piece.
4. The semiconductor package of claim 1 , wherein the first dummy structure and the semiconductor chip are disposed in a side-by-side manner.
5. The semiconductor package of claim 1 , wherein the core member comprises a distribution layer electrically connected to the connection pad.
6. The semiconductor package of claim 1 , wherein the core member further comprises a first distribution layer and a second distribution layer, disposed on two surfaces of the first insulating layer, respectively, and
the first distribution layer and the second distribution layer are electrically connected to the connection pad.
7. The semiconductor package of claim 6 , wherein the core member further comprises a second insulating layer penetrated by the first through hole, disposed on the first insulating layer, and covering the first distribution layer, a third distribution layer disposed on the second insulating layer, and a fourth distribution layer disposed on the third insulating layer,
the third distribution layer and the fourth distribution layer are electrically connected to the connection pad, and
the third insulating layer covers the second distribution layer.
8. The semiconductor package of claim 7 , wherein the first insulating layer has a thickness greater than a thickness of the second and a thickness of the portion of the third insulating layers covering the first dummy structure.
9. A semiconductor package comprising:
a core member including insulating layers stacked on each other and having a first through hole penetrating through the insulating layers of the core member, the core member including a second through hole;
a semiconductor chip disposed in the first through hole, and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface;
an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filling at least a portion of the first through hole;
a first dummy structure at least partially embedded in the core member and spaced apart from the encapsulant at least by one of the insulating layers of the core member;
a second dummy structure at least partially embedded in the core member and spaced apart from the encapsulant at least by the one of the insulating layers of the core member; and
a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad,
wherein the first dummy structure is electrically insulated from the redistribution layer of the connection member,
an arrangement of the semiconductor chip, the first dummy structure and the second dummy structure is configured to reduce a package-level warpage, and
the one of the insulating layers fills at least a portion of the second through hole, and the one of the insulating layers having a portion covering at least a portion of the second dummy structure to separate the second dummy structure from the encapsulant.
10. The semiconductor package of claim 9 , wherein a body of the semiconductor chip and the first dummy structure are made of a semiconductor material.
11. The semiconductor package of claim 9 , wherein the core member comprises a distribution layer electrically connected to the connection pad of the semiconductor chip.
12. The semiconductor package of claim 9 , wherein another of the insulating layers of the core member has a second through hole, and
the first dummy structure is disposed in the second through hole and is covered by the one of the insulating layers.
13. The semiconductor package of claim 9 , wherein
the first dummy structure is partially embedded in the one of the insulating layers of the core member, and
a surface of the first dummy structure is exposed from the one of the insulating layers and is in contact with another of the insulating layers of the core member.
14. The semiconductor package of claim 9 , wherein the first dummy structure is partially embedded in the one of the insulating layers of the core member, and
the first dummy structure are spaced apart from the encapsulant by the one of the insulating layers of the core member and another of the insulating layers of the core member disposed on the one of the insulating layers.
15. The semiconductor package of claim 9 , further comprising:
a passivation layer disposed on the connection member and having an opening exposing at least a portion of the redistribution layer;
an under-bump metal layer disposed on the opening of the passivation layer, and electrically connected to the exposed at least portion of the redistribution layer; and
an electrical connection structure disposed on the passivation layer, and connected to the under-bump metal layer to be electrically connected to the exposed at least portion of the redistribution layer.
16. The semiconductor package of claim 9 , wherein the first dummy structure is located in a fan-out region with respect to the semiconductor chip.
17. A semiconductor package comprising:
a core member having a first through hole, and including a first insulating layer having a second through hole;
a first dummy structure disposed in the second through hole of the first insulating layer of the core member;
a semiconductor chip disposed in the first through hole, and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface;
an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filling at least a portion of the first through hole; and
a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad,
wherein the first dummy structure is electrically insulated from the semiconductor chip,
the core member further including a third insulating layer penetrated by the first through hole, and
the third insulating layer covers at least a portion of the first insulating layer and fills at least a portion of the second through hole of the first insulating layer of the core member, and having a portion covering the first dummy structure to separate the first dummy structure from the encapsulant, and the first insulating layer has third through holes spaced apart from the second through hole,
the semiconductor package further includes second dummy structures disposed in the third through holes, respectively,
the second dummy structures are spaced apart from the encapsulant by the third insulating layer, and
when the core member and the first and second dummy structures are cut into planes parallel to the inactive surface of the semiconductor chip, a sum of planar areas of the first and second dummy structures is greater than a planar area of the core member.
18. A semiconductor package comprising:
a core member including first and second insulating layers stacked on each other and including a first through hole penetrating through the first and second insulating layers, the core member including a second through hole;
a semiconductor chip disposed in the first through hole, and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface;
an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filling at least a portion of the first through hole;
a first dummy structure partially embedded in one of the first and second insulating layers and having one surface exposed from the one of the first and second insulating layers;
a second dummy structure partially embedded in the one of the first and second insulating layers and having one surface exposed from the one of the first and second insulating layers; and
a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad,
wherein the first dummy structure is electrically insulated from the semiconductor chip, is spaced apart from the encapsulant at least by the one of the first and second insulating layers, and the first dummy structure is electrically insulated from the redistribution layer of the connection member,
an arrangement of the semiconductor chip, the first dummy structure and the second dummy structure is configured to reduce a package-level warpage, and
the second insulating layer fills at least a portion of the second through hole, and the second insulating layer having a portion covering at least a portion of the second dummy structure to separate the second dummy structure from the encapsulant.
19. The semiconductor package of claim 18 , wherein the first dummy structure is partially embedded in the second insulating layer,
the core member further includes a first distribution layer embedded in the first insulating layer in such a manner that a lower surface of the first distribution layer is exposed, a second distribution layer disposed on a side of the first insulating layer opposing a side of the first insulating layer in which the first distribution layer is embedded, and a third distribution layer disposed on the second insulating layer, and
the first to third distribution layers are electrically connected to the connection pad.
20. The semiconductor package of claim 19 , wherein a lower surface of the first insulating layer has a step with respect to the lower surface of the first distribution layer.
21. The semiconductor package of claim 18 , wherein the first dummy structure is partially embedded in the first insulating layer,
the core member further includes a first distribution layer embedded in the first insulating layer in such a manner that a lower surface of the first distribution layer is exposed, a second distribution layer disposed on a side of the first insulating layer opposing a side of the first insulating layer in which the first distribution layer is embedded, and a third distribution layer disposed on the second insulating layer,
the first to third distribution layers are electrically connected to the connection pad, and the first and second insulating layers are disposed between the first dummy structure and the encapsulant.
22. The semiconductor package of claim 21 , wherein a lower surface of the first insulating layer has a step with respect to the lower surface of the first distribution layer.
23. The semiconductor package of claim 18 , wherein the first dummy structure comprises silicon.
24. The semiconductor package of claim 18 , wherein the first dummy structure is a silicon piece.
25. A semiconductor package comprising:
a core member including first and second insulating layers stacked on each other and including a first through hole penetrating through the first and second insulating layers, the core member including a second through hole;
a semiconductor chip disposed in the through hole, and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface;
an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filling at least a portion of the through hole;
a first dummy structure partially embedded in one of the first and second insulating layers and having one surface exposed from the one of the first and second insulating layers;
a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad; and
second dummy structures partially embedded in the one of the first and second insulating layers and each having a surface exposed from the one of the first and second insulating layers, wherein the second dummy structures are electrically insulated from the semiconductor chip and are spaced apart from the encapsulant at least by the one of the first and second insulating layers, and when the core member and the first and second dummy structures are cut into planes parallel to the inactive surface of the semiconductor chip, a sum of planar areas of the first and second dummy structures is greater than a planar area of the core member,
wherein the first dummy structure is electrically insulated from the semiconductor chip and is spaced apart from the encapsulant at least by the one of the first and second insulating layers, and
the second insulating layer fills at least a portion of the second through hole, and the second insulating layer having a portion covering at least a portion of one second dummy structure of the second dummy structures to separate the one second dummy structure from the encapsulant.
26. A semiconductor package comprising:
a core member including insulating layers stacked on each other and having a first through hole penetrating through the insulating layers of the core member, the core member including a second through hole;
a semiconductor chip disposed in the first through hole, and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface;
an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filling at least a portion of the first through hole;
a first dummy structure at least partially embedded in the core member and spaced apart from the encapsulant at least by one of the insulating layers of the core member; and
a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad,
wherein the first dummy structure is electrically insulated from the redistribution layer of the connection member,
the semiconductor package is a fan-out semiconductor package, and the fan-out semiconductor package is configured to reduce a package-level warpage through a similarity of a first thermal expansion coefficient of the semiconductor chip and a second thermal expansion coefficient of the first dummy structure, and
the second insulating layer fills at least a portion of the second through hole, and the second insulating layer having a portion covering at least a portion of one second dummy structure of the second dummy structures to separate the one second dummy structure from the encapsulant.
27. A semiconductor package comprising:
a core member including insulating layers stacked on each other and having a first through hole penetrating through the insulating layers of the core member, the core member including a second through hole;
a semiconductor chip disposed in the first through hole, and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface;
an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filling at least a portion of the first through hole;
a first dummy structure at least partially embedded in the core member and spaced apart from the encapsulant at least by one of the insulating layers of the core member; and
a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad,
wherein the first dummy structure is electrically insulated from the redistribution layer of the connection member,
the semiconductor package is configured with a symmetric arrangement of a plurality of dummy structures surrounding the semiconductor chip, the plurality of dummy structures includes the first dummy structure and at least one other dummy structure, the symmetric arrangement is configured to offset from each other a plurality of warpages occurring locally in a region of a semiconductor package region, whereby differences in thermal expansion coefficients of components within the semiconductor package are significantly reduced, and the symmetric arrangement is configured to reduce a warpage of the semiconductor package at a package level, and
the one of the insulating layers fills at least a portion of the second through hole, and the one of the insulating layers having a portion covering at least a portion of a second dummy structure to separate the second dummy structure from the encapsulant.