Method and system for facilitating high-capacity shared memory using DIMM from retired servers

1. A computer-implemented method for facilitating a shared memory, the method comprising:

receiving, by a computing device, an I/O request, wherein a plurality of memory expansion devices are fixed to a motherboard of the computing device, wherein a first memory expansion device includes a first set of memory modules and further includes a first interface which is distinct from a memory bus;

determining, by a microprocessor of the computing device, whether the I/O request is to be processed by the first memory expansion device or by a memory module of the computing device; and

in response to determining that the I/O request is to be processed by the first memory expansion device:

transmitting, by the computing device to the first memory expansion device, via the first interface of the first memory expansion device, the I/O request to be executed by the first memory expansion device;

processing, by a controller of the first memory expansion device, the I/O request, which involves performing a cyclic redundancy check, a data placement procedure, a volatile memory management procedure, and an error correction code encoding on the data associated with the I/O request to obtain processed data;

transmitting, by the controller via a second interface of the first memory expansion device, the I/O request including the processed data to a selected memory module of the first set of memory modules; and

executing, by the selected memory module, the I/O request, based on the processed data, thereby allowing the computer system to expand memory capacity beyond memory slots available on the memory bus.

2. The method of claim 1 , further comprising:

selecting, by the controller, the first memory expansion device to which the I/O request is to be transmitted.

3. The method of claim 1 , wherein processing the I/O request further comprises:

performing a management procedure for the first set of memory modules.

4. The method of claim 1 , wherein the first interface is a Peripheral Component Interconnect Express (PCIe) interface between a requesting host and the controller, and

wherein the second interface is a dynamic random access memory (DRAM) dual in-line memory module (DIMM) interface between the controller and the memory modules.

5. The method of claim 1 , wherein the first memory expansion device is coupled to the computing device, which includes:

a set of ports;

a second set of memory modules;

a set of controllers for the second set of memory modules;

a set of microprocessors;

a switch; and

a set of lanes.

6. The method of claim 5 , wherein prior to the first memory expansion device receiving the I/O request, the method further comprises:

receiving, by the computing device via a port, the I/O request;

determining, by a microprocessor of the computing device, that the I/O request is to be processed by the first memory expansion device; and

transmitting, via the switch and a selected lane, the I/O request to the first memory expansion device to be executed by the first memory expansion device.

7. The method of claim 1 , wherein the plurality of memory expansion devices attached to or coupled to the computing device.

8. The method of claim 5 , further comprising:

receiving, by the computing device via a port, a second I/O request;

determining, by a microprocessor of the computing device, that the second I/O request is to be processed by a memory module of the second set of memory modules; and

executing, by the memory module of the second set of memory modules, the second I/O request.

9. A memory expansion device for facilitating a shared memory, the memory expansion device comprising:

a first interface which is distinct from a memory bus, wherein the memory expansion device is fixed to a motherboard of a computing device via the first interface;

control circuitry;

a second interface; and

a first set of memory modules coupled to the control circuitry via the second interface;

wherein the control circuitry is configured to:

receive, via the first interface, an I/O request;

process the I/O request, which involves performing a cyclic redundancy check, a data placement procedure, a volatile memory management procedure, and an error correction code encoding on the data associated with the I/O request to obtain processed data; and

transmit, via the second interface, the I/O request including the processed data to a selected memory module of the first set of memory modules,

wherein prior to the control circuitry receiving the I/O request, a microprocessor of the computing device is configured to:

determine whether the I/O request is to be processed by the memory expansion device or by a memory module of the computing device; and

in response to determining that the I/O request is to be processed by the memory expansion device, transmit the I/O request to the control circuitry to be executed by the memory expansion device; and

wherein the selected memory module is configured to execute, based on the processed data, the I/O request, thereby allowing the computing device to expand memory capacity beyond memory slots available on the memory bus.

10. The memory expansion device of claim 9 , wherein the control circuitry is further configured to:

select the memory module to which the I/O request is to be transmitted.

11. The memory expansion device of claim 9 , wherein in processing the I/O request, the control circuitry is further configured to:

performing a management procedure for the first set of memory modules.

12. The memory expansion device of claim 9 , wherein the first interface is a Peripheral Component Interconnect Express (PCIe) interface between a requesting host and the controller, and

wherein the second interface is a dynamic random access memory (DRAM) dual in-line memory module (DIMM) interface between the controller and the memory modules.

13. The memory expansion device of claim 9 , wherein the memory expansion device is coupled to a computing device which includes:

a set of ports;

a second set of memory modules;

a set of controllers for the second set of memory modules;

a set of microprocessors;

a switch; and

a set of lanes.

14. The memory expansion device of claim 13 , wherein prior to the control circuitry receiving the I/O request:

the microprocessor of the computing device is further configured to receive, via a port, the I/O request and transmit, via the switch and a selected lane, the I/O request to the memory expansion device to be executed by the memory expansion device.

15. The memory expansion device of claim 13 , wherein the memory expansion device is one of a plurality of memory expansion devices attached to or coupled to the computing device.

16. The memory expansion device of claim 13 , wherein the computing device is further configured to:

receive, via a port, a second I/O request;

wherein the microprocessor of the computing device is further configured to determine that the second I/O request is to be processed by a memory module of the second set of memory modules; and

wherein the memory module of the second set of memory modules is configured to execute the second I/O request.

17. A computer system for facilitating a shared memory, the system comprising:

a processor;

a volatile memory; and

a memory expansion device which is fixed to a motherboard of the computer system, includes a first set of memory modules and further includes a first interface which is distinct from a memory bus:

a first communication module configured to receive an I/O request via the first interface;

a request-processing module configured to process the I/O request, which involves performing a cyclic redundancy check, a data placement procedure, a volatile memory management procedure, and an error correction code encoding or decoding on the data associated with the I/O request to obtain processed data;

a memory-selecting module configured to select a memory module to which the I/O request is to be sent,

wherein the first communication module is further configured to transmit, via a second interface, the I/O request including the processed data to the selected memory module; and

wherein prior to the first communication module receiving the I/O request, the computing system further includes an IP DRAM control layer, which includes:

a second communication module configured to receive, via a port, the I/O request;

determine whether the I/O request is to be processed by the memory expansion device or by a memory module of the computer system; and

wherein the second communication module is further configured to, in response to determining by an IP DRAM-processing module that the I/O request is to be processed by the memory expansion device, transmit the I/O request to the first communication module to be executed by the memory expansion device; and

a request-executing module configured to execute, by the selected memory module, the I/O request, based on the processed data, thereby allowing the computer system to expand memory capacity beyond memory slots available on the memory bus.

18. The computer system of claim 17 , wherein the request-processing module is further configured to:

performing a management procedure for the first set of memory modules.

19. The computer system of claim 17 , wherein the memory expansion device is coupled to a computing device which includes:

a set of ports;

a second set of memory modules;

a set of controllers for the second set of memory modules;

a set of microprocessors;

a switch; and

a set of lanes.

20. The computer system of claim 19 ,

wherein the second communication module of the IP DRAM layer is further configured to transmit, via the switch and a selected lane, the I/O request to the memory expansion device to be executed by the memory expansion device.