Method for reducing contact resistance in semiconductor structures
Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer.
1. A method, comprising:
forming a fin over a substrate;
forming, on the fin, a gate structure having a sidewall;
forming a sidewall spacer adjacent to the sidewall;
doping a source/drain (S/D) region adjacent to the sidewall spacer;
depositing a layer of doped amorphous material over the gate structure, the sidewall spacer, and the S/D region; and
crystallizing a portion of the layer of doped amorphous material to form a region of crystallized material that comprises a doping concentration higher than a doping concentration of the S/D region.
2. The method of claim 1 , wherein the substrate is a bulk silicon wafer.
3. The method of claim 1 , wherein forming the gate structure comprises forming a gate dielectric on the fin, and forming a gate electrode over the gate dielectric.
4. The method of claim 1 , wherein forming the sidewall spacer comprises depositing a spacer material in physical contact with at least a portion of the gate structure.
5. The method of claim 1 , wherein doping the S/D region comprises implanting at least one dopant species into the fin.
6. The method of claim 1 , wherein doping the S/D region comprises forming a recess in the fin and epitaxially growing a material in the recess.
7. The method of claim 1 , wherein depositing the layer of doped amorphous material comprises depositing a layer of n-doped amorphous silicon.
8. The method of claim 1 , wherein depositing the layer of doped amorphous material comprises depositing a layer of n-doped amorphous silicon having a doping concentration in a range of about 5×10 20 atoms/cm 3 to about 7×10 21 atoms/cm 3 .
9. The method of claim 1 , wherein depositing the layer of doped amorphous material comprises depositing a layer of n-doped amorphous silicon germanium.
10. The method of claim 1 , wherein depositing the layer of doped amorphous material comprises depositing a layer of n-doped amorphous silicon germanium having a doping concentration in the range of about 5×10 20 atoms/cm 3 to about 7×10 21 atoms/cm 3 .
11. The method of claim 1 , wherein crystallizing the portion of the layer of doped amorphous silicon comprises performing a solid phase epitaxial regrowth at a temperature of about 600° C.
12. The method of claim 11 , further comprising removing the doped amorphous silicon after the solid phase epitaxial regrowth.
13. The method of claim 9 , wherein crystallizing the portion of the layer of doped amorphous silicon germanium comprises performing a solid phase epitaxial regrowth at a temperature of about 500° C.
14. The method of claim 13 , further comprising removing the doped amorphous silicon germanium after the solid phase epitaxial regrowth.
15. The method of claim 1 further comprising:
depositing a metal silicide on the crystallized material; and
forming a contact plug over the metal silicide.
16. A method, comprising:
forming a fin over a substrate;
forming, on the fin, a gate structure on the fin with a sidewall;
forming a sidewall spacer adjacent to the sidewall;
doping a source/drain (S/D) region adjacent to the sidewall spacer, a portion of the S/D region being disposed in the fin;
depositing a layer of doped amorphous material over the gate structure, the sidewall spacer, and the S/D region; and
crystallizing a portion of the layer of doped amorphous material to form a region of crystallized material that comprises a doping concentration higher than a doping concentration of the S/D region.
17. The method of claim 16 , wherein the substrate is a bulk silicon wafer.
18. The method of claim 16 , wherein forming the gate structure comprises forming a gate dielectric on the fin, and forming a gate electrode over the gate dielectric.
19. The method of claim 16 , wherein forming the sidewall spacer comprises depositing a spacer material in physical contact with at least a portion of the gate structure.
20. A method, comprising:
forming a fin over a substrate;
forming, over the fin, a first gate structure with a first sidewall and a first spacer formed thereon;
forming, over the fin, a second gate structure with a second sidewall and a second spacer formed thereon, the second spacer opposing the first spacer;
doping a source/drain (S/D) region in the fin between the first spacer and the second spacer;
depositing a layer of doped amorphous material over the gate structure, the sidewall spacer, and the S/D region; and
crystallizing a portion of the layer of doped amorphous material to form a region of crystallized material that comprises a doping concentration higher than a doping concentration of the S/D region.