Electrostatic discharge protection circuit

1. An electrostatic discharge (ESD) protection circuit coupled between first and second power supply buses, comprising:

a detection circuit;

a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor;

a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor;

a resistor having a first end coupled to the first bus and a second end coupled to gates of the first and second n-type transistors so as to delay a pulse signal provided on the first bus from turning on the first and second n-type transistors; and

a bypass circuit, coupled to the pull-up and pull-down circuits,

wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

2. The circuit of claim 1 , wherein the detection circuit comprises at least a first resistor and at least a capacitor coupled to each other at a first node.

3. The circuit of claim 2 , wherein the capacitor comprises a transistor that comprises a drain end, a source end, and a body end respectively coupled to the second power supply bus, and a gate end coupled to the first node.

4. The circuit of claim 2 , wherein the pull-up circuit, coupled between the first and second power supply buses, further comprises at least a third n-type transistor and at least a second resistor, and wherein the first n-type transistor is gated by a voltage level at the first node, and the third n-type transistor is gated by a voltage level at a second node that is commonly coupled by the first n-type transistor and the second resistor.

5. The circuit of claim 2 , wherein the second n-type transistor of the pull-down circuit is gated by the voltage level at the first node.

6. The circuit of claim 2 , wherein the second n-type transistor of the pull-down circuit and the third n-type transistor of the pull-up circuit is coupled at a third node.

7. The circuit of claim 6 , wherein the bypass circuit comprises at least a fourth n-type transistor that is gated by a voltage level as the third node.

8. The circuit of claim 7 , wherein when the ESD event is present on the first power supply bus, the voltage level at the first node corresponds to a low logic state such that the first n-type transistor of the pull-up circuit and the third n-type transistor of the pull-down circuit are turned off, the voltage level at the second node corresponds to a high logic state such that the second n-type transistor of the pull-up circuit is turned on, and the voltage level at the third node corresponds to a high logic state to turn on the fourth n-type transistor so as to provide the discharging path.

9. The circuit of claim 1 , wherein the first power supply bus is configured to provide a first supply voltage and the second power supply bus is configured to provide a second supply voltage, the first supply voltage being higher than the second supply voltage.

10. An electrostatic discharge (ESD) protection circuit coupled between first and second power supply buses, comprising:

a detection circuit comprising a first resistor and a capacitor coupled to each other at a first node;

a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor;

a pull-down circuit, coupled to the pull-up circuit, comprising a second n-type transistor; and

a bypass circuit, coupled to the pull-up and pull-down circuits,

wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses, and wherein the first resistor and the capacitor are configured to delay a pulse signal provided on the first bus from turning on the first and second n-type transistors.

11. The circuit of claim 10 , wherein the capacitor comprises a transistor that comprises a drain end, a source end, and a body end respectively coupled to the second power supply bus.

12. The circuit of claim 10 , wherein the pull-up circuit, coupled between the first and second power supply buses, further comprises a third n-type transistor and a second resistor, and wherein the first n-type transistor is gated by a voltage level at the first node, and the third n-type transistor is gated by a voltage level at a second node that is commonly coupled by the first n-type transistor and the second resistor.

13. The circuit of claim 10 , wherein the second n-type transistor of the pull-down circuit is gated by the voltage level at the first node.

14. The circuit of claim 10 , wherein the second n-type transistor of the pull-down circuit and the third n-type transistor of the pull-up circuit is coupled at a third node.

15. The circuit of claim 14 , wherein the bypass circuit comprises a fourth n-type transistor that is gated by a voltage level as the third node.

16. The circuit of claim 15 , wherein when the ESD event is present on the first power supply bus, the voltage level at the first node corresponds to a low logic state such that the first n-type transistor of the pull-up circuit and the third n-type transistor of the pull-down circuit are turned off, the voltage level at the second node corresponds to a high logic state such that the second n-type transistor of the pull-up circuit is turned on, and the voltage level at the third node corresponds to a high logic state to turn on the fourth n-type transistor so as to provide the discharging path.

17. The circuit of claim 10 , wherein the first power supply bus is configured to provide a positive supply voltage and the second power supply bus is configured to provide a ground voltage.

18. A method to operate an electrostatic discharge (ESD) protection circuit, comprising:

detecting a presence of an ESD pulse signal on a first power supply bus;

delaying the ESD pulse signal to charge a first node to cause the first node to be at a low logic state thereby turning off first and second n-type transistors;

charging a second node to cause the second node to be at a high logic state through a first resistor thereby turning on a third n-type transistor;

charging a third node to cause the third node to be at the high logic state through the third n-type transistor thereby turning on a fourth n-type transistor coupled between the first power supply bus and a second power supply bus so as to discharge the ESD pulse signal from the first power supply bus to the second power supply bus.

19. The method of claim 18 , further comprising:

delivering a positive supply voltage from the first power supply bus to a coupled circuit while the ESD pulse signal is discharged from the first power supply bus to the second power supply bus.

20. The method of claim 18 , further comprising:

detecting a lack of the ESD pulse signal on the first power supply bus;

charging the first node to cause the first node to be at the high logic state thereby turning on the first and second n-type transistors;

discharging a gate end of the third n-type transistor through the turned-off first n-type transistor thereby turning off the third n-type transistor; and

discharging the third node through the second n-type transistor to cause the third node to be at the low logic state thereby turning off the fourth n-type transistor.