Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating
A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.
1. A semiconductor memory array comprising:
a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include:
a floating body region;
a non-volatile memory comprising a bipolar resistive change element;
wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on resistivity of said bipolar resistive change element, upon restoration of power to said memory cell;
wherein said array is configured to perform a restore operation on said at least two of said memory cells in parallel.
2. The semiconductor memory array of claim 1 , wherein said memory cell functions as volatile memory upon said restoration of power to said memory cell.
3. The semiconductor memory array of claim 1 , wherein said floating body region is configured to a predetermined state prior to being charged based on resistivity of said bipolar resistive change element.
4. The semiconductor memory array of claim 1 , wherein said bipolar resistive change element is configured to a predetermined resistivity after said floating body region is charged to a level based on resistivity of said bipolar resistive change element.
5. The semiconductor memory array of claim 1 , further comprising a first region in electrical contact with said floating body region and a second region spaced apart from said first region and in electrical contact with said floating body region.
6. The semiconductor memory array of claim 1 , wherein said bipolar resistive change element comprises a material selected from at least one of: transition metal oxide materials, ferroelectric materials and ferromagnetic materials.
7. The semiconductor memory array of claim 1 , wherein said bipolar resistive change element is electrically connected to said floating body region and a distance between said bipolar resistive change element and said bipolar device, when electrically connected, is in the range from about 90 nm to 1 μm.
8. The semiconductor memory array of claim 1 , further comprising an addressable line electrically connected to said bipolar resistive change element.
9. The semiconductor memory array of claim 8 , wherein said bipolar resistive change element further comprises a conductive material element interconnecting said addressable line and said bipolar resistive change material.
10. The semiconductor memory array of claim 1 comprising a three-dimensional structure comprising a fin structure comprising said floating body region, extending substantially perpendicular to, and above a top surface of a substrate.
11. An integrated circuit comprising:
a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include:
a floating body region;
a non-volatile memory comprising a bipolar resistive change element;
wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on resistivity of said bipolar resistive change element, upon restoration of power to said memory cell; and
a circuit configured to perform a restore operation on said at least two of said memory cells in parallel.
12. The integrated circuit of claim 11 , wherein said memory cell functions as volatile memory upon said restoration of power to said memory cell.
13. The integrated circuit of claim 11 , wherein said floating body region is configured to a predetermined state prior to being charged based on resistivity of said bipolar resistive change element.
14. The integrated circuit of claim 11 , wherein said bipolar resistive change element is configured to a predetermined resistivity after said floating body region is charged to a level based on resistivity of said bipolar resistive change element.
15. The integrated circuit of claim 11 , further comprising a first region in electrical contact with said floating body region and a second region spaced apart from said first region and in electrical contact with said floating body region.
16. The integrated circuit of claim 11 , wherein said bipolar resistive change element comprises a material selected from at least one of: transition metal oxide materials, ferroelectric materials and ferromagnetic materials.
17. The integrated circuit of claim 11 , wherein said bipolar resistive change element is electrically connected to said floating body region and a distance between said bipolar resistive change element and said bipolar device, when electrically connected, is in the range from about 90 nm to 1 μm.
18. The integrated circuit of claim 11 , further comprising an addressable line electrically connected to said bipolar resistive change element.
19. The integrated circuit of claim 18 , wherein said bipolar resistive change element further comprises a conductive material element interconnecting said addressable line and said bipolar resistive change material.
20. The integrated circuit of claim 11 comprising a three-dimensional structure comprising a fin structure comprising said floating body region, extending substantially perpendicular to, and above a top surface of a substrate.