Low thermal budget top source and drain region formation for vertical transistors
A method of forming a semiconductor device that includes forming a vertically orientated channel in a semiconductor fin structure that is present on a supporting substrate; and depositing a doped amorphous semiconductor material on an upper surface of the semiconductor fin structure that is opposite a base surface of the semiconductor fin structure that is in contact with the supporting substrate. The method further includes recrystallizing the doped amorphous semiconductor material with an anneal duration for substantially a millisecond duration or less to provide a doped polycrystalline source and/or drain region at the upper surface of the semiconductor fin structure.
1. A method of forming a semiconductor device comprising:
forming a vertically orientated channel in a semiconductor fin structure that is present on a supporting substrate;
forming a gate structure adjacent sidewalls of the semiconductor fin over source/drain regions;
forming a first spacer between the source/drain regions and the gate structure;
forming a second spacer over the gate structure, such that the first and second spacers are on opposed ends of the gate structure;
depositing a doped amorphous semiconductor material on an upper surface of the semiconductor fin structure that is opposite a base surface of the semiconductor fin structure that is in contact with the supporting substrate; and
recrystallizing the doped amorphous semiconductor material with an anneal duration for substantially a millisecond duration or less to provide a doped polycrystalline source and/or drain region at the upper surface of the semiconductor fin structure.
2. The method of claim 1 , wherein said depositing said doped amorphous semiconductor material comprises physical vapor deposition (PVD).
3. The method of claim 2 , wherein said doped amorphous semiconductor material is of a composition selected from the group consisting of amorphous silicon, amorphous silicon germanium, amorphous germanium and combinations thereof.
4. The method of claim 3 , wherein the doped amorphous semiconductor material comprises a dopant selected from the group consisting of boron, arsenic, phosphorus, gallium, antimony and combinations thereof.
5. The method of claim 1 , wherein the anneal temperature ranges from 700° to 1200° C.
6. The method of claim 1 , wherein said recrystallizing comprises an anneal process selected from the group consisting of laser annealing, flash annealing, and combinations thereof.
7. The method of claim 1 , further comprising ion implantation of the upper surface of the semiconductor fin structure with an n-type or p-type dopant prior to said depositing said doped amorphous semiconductor material.
8. A method of forming a semiconductor device comprising:
forming a plurality of vertically orientated channel regions each present in a semiconductor fin structure that is present on a supporting substrate;
forming a gate structure adjacent sidewalls of the semiconductor fin and over source/drain regions;
forming a first spacer between teh source/drain regions and the gate structure;
forming a second spacer over the gate structure, such that the first and second spacers are on opposed ends of the gate structure;
depositing a doped amorphous semiconductor material on an upper surface of each of said semiconductor fin structure for the plurality of vertically orientated channel regions that are opposite a base surface of the semiconductor fin structure that is in contact with the supporting substrate; and
recrystallizing the doped amorphous semiconductor material with an anneal to provide a doped polycrystalline source and/or drain region at the upper surface of the semiconductor fin structure, wherein the doped polycrystalline source and/or drain region has a planar upper surface and provides a merging structure between adjacent fin structures that provide the plurality of vertically orientated channel regions.
9. The method of claim 8 , wherein said depositing said doped amorphous semiconductor material comprises physical vapor deposition (PVD).
10. The method of claim 9 , wherein said doped amorphous semiconductor material is of a composition selected from the group consisting of amorphous silicon, amorphous silicon germanium, amorphous germanium and combinations thereof.
11. The method of claim 10 , wherein the doped amorphous semiconductor material comprises a dopant selected from the group consisting of boron, arsenic, phosphorus, gallium, antimony and combinations thereof.
12. The method of claim 9 , wherein the anneal temperature ranges from 600° to 1250° C.
13. The method of claim 8 , wherein said recrystallizing comprises an anneal process selected from the group consisting of laser annealing, flash annealing, and combinations thereof.
14. The method of claim 8 , further comprising ion implantation of the upper surface of the semiconductor fin structure with an n-type or p-type dopant prior to said depositing said doped amorphous semiconductor material.