Gate arrangements in quantum dot devices
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.
1. A quantum dot device, comprising:
a quantum well stack;
a first gate and an adjacent second gate above the quantum well stack; and
a gate wall between the first gate and the second gate, wherein the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.
2. The quantum dot device of claim 1 , wherein the second dielectric material includes silicon nitride.
3. The quantum dot device of claim 1 , wherein the first dielectric material includes aluminum oxide.
4. The quantum dot device of claim 1 , wherein the first dielectric material includes silicon carbide.
5. The quantum dot device of claim 1 , wherein the first dielectric material includes silicon nitride.
6. The quantum dot device of claim 1 , wherein the second dielectric material is a spacer.
7. The quantum dot device of claim 6 , wherein the first dielectric material is at least partially between the second dielectric material and the quantum well stack.
8. The quantum dot device of claim 1 , wherein the first dielectric material is at least partially between the second dielectric material and the quantum well stack.
9. The quantum dot device of claim 8 , wherein the first gate includes a first gate metal and a first gate dielectric, and the first gate dielectric is at least partially between the first gate metal and the first dielectric material.
10. The quantum dot device of claim 9 , wherein the first gate dielectric has a U-shaped cross-section.
11. The quantum dot device of claim 9 , wherein the second gate includes a second gate metal and a second gate dielectric, and the second gate dielectric is at least partially between the second gate metal and the second dielectric material.
12. The quantum dot device of claim 1 , wherein the first dielectric material has an L-shaped cross-section.
13. The quantum dot device of claim 1 , wherein the first gate includes a first gate metal, the second gate includes a second gate metal, and the first gate metal has a height that is different from a height of the second gate metal.
14. The quantum dot device of claim 1 , wherein the first gate includes a first gate metal, the second gate includes a second gate metal, and the first gate metal has a different material structure than the second gate metal.
15. The quantum dot device of claim 1 , wherein the quantum well stack includes a quantum well layer, the quantum well layer has a first strain under the first gate, a second strain under the second gate, and the first strain is different from the second strain.
16. The quantum dot device of claim 1 , wherein the quantum well stack is at least partially included in a fin.
17. The quantum dot device of claim 1 , wherein the first gate and the second gate are at least partially disposed in a trench in an insulating material above the quantum well stack.
18. A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes a quantum well stack, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, a gate wall between at least two gates, wherein the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material; and
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the plurality of gates.
19. The quantum computing device of claim 18 , wherein the first dielectric material has an L-shaped cross-section.
20. The quantum computing device of claim 18 , wherein the second dielectric material is a spacer.
21. A method of operating a quantum dot device, comprising:
providing electrical signals to one or more first gates above a quantum well stack as part of causing a first quantum well to form in a quantum well layer in the quantum well stack;
providing electrical signals to one or more second gates above the quantum well stack as part of causing a second quantum well to form in the quantum well layer in the quantum well stack; and
providing electrical signals to one or more third gates above the quantum well stack to (1) cause a third quantum well to form in the quantum well layer in the quantum well stack or (2) provide a potential barrier between the first quantum well and the second quantum well;
wherein at least two of the first, second, or third gates have a gate wall between them, the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material, and the first dielectric material is at least partially between the second dielectric material and the quantum well stack.
22. The method of claim 21 , wherein the first dielectric material is at least partially between the second dielectric material and a gate metal of at least one of the first, second, or third gates.