Metal/dielectric/metal hybrid hard mask to define ultra-large height top electrode for sub 60nm MRAM devices
View Patent ↗An ultra-large height top electrode for MRAM is achieved by employing a novel thin metal/thick dielectric/thick metal hybrid hard mask stack. Etching parameters are chosen to etch the dielectric quickly but to have an extremely low etch rate on the metals above and underneath. Because of the protection of the large thickness of the dielectric layer, the ultra-large height metal hard mask is etched with high integrity, eventually making a large height top electrode possible.
1. A method for etching a magnetic tunneling junction (MTJ) structure comprising:
providing a bottom electrode on a substrate;
depositing a MTJ stack on said bottom electrode;
depositing a top electrode layer having a first thickness on said MTJ stack;
forming a hybrid hard mask on said top electrode layer wherein said hybrid hard mask comprises a first dielectric mask layer having a mask thickness of more than four times said first thickness and second and third mask layers on said first dielectric mask layer, wherein said first dielectric mask layer physically contacts said top electrode layer;
forming a photo resist pattern on said hybrid hard mask;
first etching second and third mask layers of said hybrid hard mask where it is not covered by said photo resist pattern using a first etching chemistry;
thereafter second etching said hybrid hard mask where it is not covered by remaining said second and third mask layers using a second etching chemistry;
thereafter etching said top electrode where it is not covered by remaining said hybrid hard mask, wherein a portion of said first dielectric mask layer remains on patterned said top electrode after said etching of said top electrode, wherein said portion of said first dielectric mask layer has a top surface that is exposed after said etching of said top electrode, said top surface of said portion of said first dielectric mask layer facing away from said substrate; and
thereafter over etching said MTJ stack and said bottom electrode using said patterned top electrode and said portion of said first dielectric mask layer as a mask, wherein said over etching includes over etching said bottom electrode and said MTJ stack such that re-deposition material is formed on sidewalls of said bottom electrode and not on sidewalls of said MTJ stack, wherein remaining said top electrode has a second thickness no less than 80% of said first thickness after said etching of said MTJ stack.
2. The method of claim 1 wherein said top electrode layer comprises Ta, Ti, TaN, or TiN having said first thickness of greater than or equal to 100 nm and wherein after said etching said MTJ stack, said top electrode has said second thickness of greater than or equal to 80 nm.
3. The method of claim 1 wherein said first dielectric mask layer comprises silicon oxynitride (SiON) or silicon dioxide having a thickness of greater than or equal to 400 nm.
4. The method of claim 1 wherein said second mask layer comprises Ti, TiN, Ta, or TaN and has a thickness 30 to 50 nm smaller than said first thickness of said top electrode layer.
5. The method of claim 1 wherein said third mask layer comprises SiON having a thickness of between about 30 and 90 nm.
6. The method of claim 1 wherein said first etching comprises etching with a fluorine carbon based plasma which has a low carbon to fluorine ratio alone or mixed with Ar and N 2 .
7. The method of claim 1 wherein said second etching comprises etching with C 4 F 8 or CH 2 F 2 alone or mixed with Ar and/or O 2 .
8. The method of claim 1 wherein said etching said top electrode layer comprises etching with CF 4 , CHF 3 , Cl 2 , or Cl 2 mixed with BCl 3 .
9. The method of claim 1 , wherein said portion of said first dielectric mask layer is removed during said etching of said MTJ stack.
10. The method of claim 1 , wherein a first portion of a top surface of said bottom electrode is exposed after said etching of said MTJ stack.
11. The method of claim 10 , wherein said re-deposition material is further formed on a second portion of said top surface of said bottom electrode, said top surface of said bottom electrode facing away from said substrate.
12. The method of claim 1 , wherein said second mask layer includes a metal material, and
wherein said third mask layer includes a dielectric material.
13. The method of claim 1 , wherein said top electrode layer includes a material selected from the group consisting of Ta, Ti, TaN, and TiN,
wherein said first dielectric mask layer includes a material selected from the group consisting of silicon oxynitride (SiON) and silicon dioxide,
wherein said second mask layer includes a material selected from the group consisting of Ti, TiN, Ta, and TaN, and
wherein said third mask layer includes SiON.
14. The method of claim 1 , wherein said first etching of said second and third mask includes performing a reactive ion etching process.
15. The method of claim 1 , wherein a top surface of said top electrode layer is exposed after said second etching of said hybrid hard mask.
16. The method of claim 1 , wherein said substrate includes a semiconductor substrate.
17. The method of claim 1 , wherein said forming of said hybrid hard mask on said top electrode layer includes forming said hybrid mask directly on said top electrode layer such that said hybrid hard mask physically contacts said top electrode layer.
18. The method of claim 1 , wherein said second mask layer physically contacts sad first dielectric mask layer, and
wherein said third mask layer physically contacts said second mask layer.
19. The method of claim 1 , wherein said first etching of said second and third mask layers includes etching with a fluorine carbon based plasma.
20. The method of claim 1 , wherein said first etching of said second and third mask layers includes etching with a halogen based plasma.