IP Library › Granted Patent US 10,192,862
Granted Patent B2
US 10,192,862 · App. 15/902,815 · Granted Jan 29, 2019

Semiconductor device

Inventors: Kenji Sasaki (Nagaokakyo, JP); Takayuki Tsutsui (Nagaokakyo, JP); Isao Obu (Nagaokakyo, JP); Yasuhisa Yamamoto (Nagaokakyo, JP)
Assignee: Murata Manufacturing Co., Ltd.
H01L27/0255H01L24/06H01L24/17H01L24/49H01L29/0821H01L29/1004H01L29/41708H01L29/42304H03F3/213
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Quick Facts
Patent No.
US 10,192,862
App. No.
15/902,815
Granted
Jan 29, 2019
Kind
B2
Abstract

An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.

Claims (52)

1. A semiconductor device comprising:

an amplifier circuit including a semiconductor element formed on a substrate;

a protection circuit including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit; and

a pad conductive layer at least partially including a pad for connecting to a circuit outside the substrate, wherein

the pad conductive layer and the protection circuit at least partially overlap each other in plan view, and

at least one of the protection diodes includes a substantially U-shaped electrode in plan view.

2. The semiconductor device according to claim 1 , further comprising:

a ground conductor formed on the substrate,

wherein the protection circuit is connected between the output terminal of the amplifier circuit and the ground conductor.

3. The semiconductor device according to claim 1 , further comprising:

an insulating protective film covering the pad conductive layer, the insulating protective film including an opening that exposes a partial area of a surface of the pad conductive layer, the insulating protective film covering another area,

wherein the opening and the protection circuit at least partially overlap each other in plan view.

4. The semiconductor device according to claim 3 , further comprising:

a bump formed on the pad conductive layer on a bottom surface of the opening.

5. The semiconductor device according to claim 4 , wherein a planar shape of the bump is substantially rectangular with rounded corners.

6. The semiconductor device according to claim 1 , wherein:

the plurality of protection diodes constitute a diode array folded back halfway in plan view,

each of the plurality of protection diodes includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type that is opposite to the first conductivity type, the second semiconductor layer being formed in a partial area of an upper surface of the first semiconductor layer, and

the substantially U-shaped electrode is ohmic-connected to the upper surface of the first semiconductor layer and has a planar shape in which the second semiconductor layer is held in a width direction of the diode array in plan view.

7. The semiconductor device according to claim 1 , wherein the semiconductor element is formed of compound semiconductor.

8. The semiconductor device according to claim 2 , further comprising:

an insulating protective film covering the pad conductive layer, the insulating protective film including an opening that exposes a partial area of a surface of the pad conductive layer, the insulating protective film covering another area,

wherein the opening and the protection circuit at least partially overlap each other in plan view.

9. The semiconductor device according to claim 2 , wherein the plurality of protection diodes constitute a diode array folded back halfway in plan view, and part of the protection circuit is arranged outside the pad conductive layer.

10. The semiconductor device according to claim 3 , wherein the plurality of protection diodes constitute a diode array folded back halfway in plan view, and part of the protection circuit is arranged outside the pad conductive layer.

11. The semiconductor device according to claim 4 , wherein the plurality of protection diodes constitute a diode array folded back halfway in plan view, and part of the protection circuit is arranged outside the pad conductive layer.

12. The semiconductor device according to claim 5 , wherein the plurality of protection diodes constitute a diode array folded back halfway in plan view, and part of the protection circuit is arranged outside the pad conductive layer.

13. The semiconductor device according to claim 2 , wherein:

the plurality of protection diodes constitute a diode array folded back halfway in plan view,

each of the plurality of protection diodes includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type that is opposite to the first conductivity type, the second semiconductor layer being formed in a partial area of an upper surface of the first semiconductor layer, and

the substantially U-shaped electrode is ohmic-connected to the upper surface of the first semiconductor layer and has a planar shape in which the second semiconductor layer is held in a width direction of the diode array in plan view.

14. The semiconductor device according to claim 3 , wherein:

the plurality of protection diodes constitute a diode array folded back halfway in plan view,

each of the plurality of protection diodes includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type that is opposite to the first conductivity type, the second semiconductor layer being formed in a partial area of an upper surface of the first semiconductor layer, and

the substantially U-shaped electrode is ohmic-connected to the upper surface of the first semiconductor layer and has a planar shape in which the second semiconductor layer is held in a width direction of the diode array in plan view.

15. The semiconductor device according to claim 4 , wherein:

the plurality of protection diodes constitute a diode array folded back halfway in plan view,

each of the plurality of protection diodes includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type that is opposite to the first conductivity type, the second semiconductor layer being formed in a partial area of an upper surface of the first semiconductor layer, and

the substantially U-shaped electrode is ohmic-connected to the upper surface of the first semiconductor layer and has a planar shape in which the second semiconductor layer is held in a width direction of the diode array in plan view.

16. The semiconductor device according to claim 5 , wherein:

the plurality of protection diodes constitute a diode array folded back halfway in plan view,

each of the plurality of protection diodes includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type that is opposite to the first conductivity type, the second semiconductor layer being formed in a partial area of an upper surface of the first semiconductor layer, and

the substantially U-shaped electrode is ohmic-connected to the upper surface of the first semiconductor layer and has a planar shape in which the second semiconductor layer is held in a width direction of the diode array in plan view.

17. The semiconductor device according to claim 2 , wherein the semiconductor element is formed of compound semiconductor.

18. The semiconductor device according to claim 3 , wherein the semiconductor element is formed of compound semiconductor.

19. The semiconductor device according to claim 4 , wherein the semiconductor element is formed of compound semiconductor.

20. A semiconductor device comprising

an amplifier circuit including a semiconductor element formed on a substrate;

a protection circuit including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit; and

a pad conductive layer at least partially including a pad for connecting to a circuit outside the substrate, wherein

the pad conductive layer and the protection circuit at least partially overlap each other in plan view, and

the plurality of protection diodes constitute a diode array folded back halfway in plan view, and part of the protection circuit is arranged outside the pad conductive layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2018
From: SASAKI, KENJI; TSUTSUI, TAKAYUKI; OBU, ISAO; YAMAMOTO, YASUHISA
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 045010/0684 →
Priority Claims (2)
JP 2017-035871 · Feb 28, 2017 · national
JP 2017-142136 · Jul 21, 2017 · national
Continuity (1)
Related Publication 20180247926A1 · Aug 30, 2018