Capacitance coupling parameter estimation in flash memories

1. A method for capacitance coupling noise accommodation, comprising the steps of:

determining a plurality of mean voltages among a plurality of memory cells of the memory in each of a plurality of cases related to inter-cell interference;

generating a plurality of middle state mean voltages in response to the mean voltages; and

adjusting one or more threshold voltages used to read from the memory based on the middle state mean voltages to operate independently of knowledge of middle state distributions in the memory cells.

2. The method according to claim 1 , further comprising the step of:

estimating a plurality of coupling parameters in response to the mean voltages, wherein

the adjustment of the threshold voltages is further based on the coupling parameters, and

the coupling parameters comprise one or more couplings between a plurality of perturbed memory cells and a plurality of neighboring memory cells adjacent to the perturbed memory cells in the memory.

3. The method according to claim 2 , wherein the coupling parameters are determined under one or more conditions of

the memory is off-line and the coupling parameters are estimated, and

the memory is on-line and the coupling parameters are updated a plurality of times.

4. The method according to claim 3 , wherein

the memory is a flash memory configured to store at least two bits in each of the memory cells,

one of the coupling parameters represents a horizontal capacitance coupling between the perturbed memory cells and the neighboring memory cells, and

another of the coupling parameters is a vertical capacitance coupling between the perturbed memory cells and the neighboring memory cells.

5. The method according to claim 4 , wherein the middle state mean voltages comprise the mean voltage of the perturbed memory cells in an erased state.

6. The method according to claim 5 , wherein the middle state mean voltages comprise the mean voltage of the perturbed memory cells after programming a lower page and before programming an upper page in the perturbed memory cells.

7. The method according to claim 6 , wherein the cases include

a final voltage case,

a no inter-cell interference case,

a vertical capacitance coupling case, and

a horizontal capacitance coupling case.

8. The method according to claim 7 , wherein the mean voltages are determined by writing random data to the memory cells and reading the random data from the memory cells.

9. The method according to claim 8 , wherein the steps are implemented in a solid-state drive.

10. An apparatus comprising:

an interface configured to process a plurality of read/write operations to/from a memory; and

a control circuit configured to

determine a plurality of mean voltages among a plurality of memory cells of the memory in each of a plurality of cases related to inter-cell interference,

generate a plurality of middle state mean voltages in response to the mean voltages, and

adjust one or more threshold voltages used to read from the memory based on the middle state mean voltages to operate independently of knowledge of middle state distributions in the memory cells.

11. The apparatus according to claim 10 , wherein the control circuit is further configured to

estimate a plurality of coupling parameters in response to the mean voltages, wherein

the adjustment of the threshold voltages is further based on the coupling parameters, and

the coupling parameters comprise one or more couplings between a plurality of perturbed memory cells and a plurality of neighboring memory cells adjacent to the perturbed memory cells in the memory.

12. The apparatus according to claim 11 , wherein the coupling parameters are determined under one or more conditions of

the memory is off-line and the coupling parameters are estimated by the control circuit, and

the memory is on-line and the coupling parameters are updated a plurality of times by the control circuit.

13. The apparatus according to claim 11 , wherein

the memory is a flash memory configured to store at least two bits in each of the memory cells,

one of the coupling parameters represents a horizontal capacitance coupling between the perturbed memory cells and the neighboring memory cells, and

another of the coupling parameters is a vertical capacitance coupling between the perturbed memory cells and the neighboring memory cells.

14. The apparatus according to claim 11 , wherein the middle state mean voltages comprise the mean voltage of the perturbed memory cells in an erased state.

15. The apparatus according to claim 11 , wherein the middle state mean voltages comprise the mean voltage of the perturbed memory cells after programming a lower page and before programming an upper page in the perturbed memory cells.

16. The apparatus according to claim 10 , wherein the cases include

a final voltage case,

a no inter-cell interference case,

a vertical capacitance coupling case, and

a horizontal capacitance coupling case.

17. The apparatus according to claim 10 , wherein the mean voltages are determined by writing random data to the memory cells and reading the random data from the memory cells.

18. The apparatus according to claim 10 , wherein the interface and the control circuit are implemented as part of a solid-state drive.

19. An apparatus comprising:

a memory configured to store data; and

a controller configured to

determine a plurality of mean voltages among a plurality of memory cells of the memory in each of a plurality of cases related to inter-cell interference,

generate a plurality of middle state mean voltages in response to the mean voltages, and

adjust one or more threshold voltages used to read from the memory based on the middle state mean voltages to operate independently of knowledge of middle state distributions in the memory cells.

20. The apparatus according to claim 19 , wherein the memory and the controller are implemented as part of a solid-state drive.