Semiconductor device and manufacturing method thereof

1. A semiconductor device, comprising:

a substrate having a first semiconductor fin and a second semiconductor fin, wherein the first semiconductor fin has a first sidewall farthest from the second semiconductor fin and a second sidewall closest to the second semiconductor fin, and the second semiconductor fin has a third sidewall closest to the first semiconductor fin;

a shallow trench isolation (STI) structure around a lower part of the first semiconductor fin and a lower part of the second semiconductor fin;

a fin spacer having a first portion laterally extending along a top surface of the STI structure, a second portion extending upwardly from the first portion of the fin spacer along the second sidewall of the first semiconductor fin, and a third portion expending upwardly from the first portion along the third sidewall of the second semiconductor fin; and

an epitaxy structure over the first semiconductor fin and the second portion of the fin spacer, the epitaxy structure having an asymmetrical cross-section that extends differently beyond the first sidewall and second sidewall of the first semiconductor fin, respectively.

2. The semiconductor device of claim 1 , wherein a portion of the epitaxy structure extends past the second sidewall of the first semiconductor fin.

3. The semiconductor device of claim 1 , wherein the epitaxy structure is further in contact with the second sidewall of the first semiconductor fin.

4. The semiconductor device of claim 1 , wherein the first semiconductor fin comprises:

a bottom portion having a first width; and

a top portion disposed between the epitaxy structure and the bottom portion, and the top portion having a second width less than the first width.

5. A semiconductor device, comprising:

a substrate having a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin;

a first epitaxy structure disposed on the first semiconductor fin, wherein a profile of the first epitaxy structure is asymmetric with respect to the first semiconductor fin;

a second epitaxy structure disposed on the second semiconductor fin, wherein a profile of the second epitaxy structure is asymmetric with respect to the second semiconductor fin, and the first epitaxy structure is separated from the second epitaxy structure; and

an shallow trench isolation (STI) structure around a lower part of the first semiconductor fin and a lower part of the second semiconductor fin;

a spacer layer forming an U-shaped pattern when viewed in a cross-section taken along a direction perpendicular to longitudinal axes of the first and second semiconductor fins, wherein the U-shaped pattern lines sidewalls of the first and second semiconductor fins and a top surface of the STI structure, and has top ends respectively capped by the first and second epitaxy structures.

6. The semiconductor device of claim 5 , wherein the spacer layer is in contact with the first semiconductor fin and the second semiconductor fin.

7. The semiconductor device of claim 5 , wherein the spacer layer has a recess therein, and the semiconductor device further comprises a dielectric material disposed in the recess of the spacer layer.

8. The semiconductor device of claim 5 , wherein a bottom surface of the first epitaxy structure and a bottom surface of the spacer layer are substantially at the same level.

9. The semiconductor device of claim 5 , wherein:

the first epitaxy structure covers a sidewall of the first semiconductor fin opposite to the second semiconductor fin; and

the second epitaxy structure covers a sidewall of the second semiconductor fin opposite to the first semiconductor fin.

10. A semiconductor device, comprising:

a substrate comprising a first semiconductor fin and a second semiconductor fin, wherein the first semiconductor fin comprises a first sidewall distal to the second semiconductor fin and a second sidewall facing the second semiconductor fin, and the second semiconductor fin has a third sidewall facing the first semiconductor fin;

a shallow trench isolation (STI) structure around a lower part of the first semiconductor fin and a lower part of the second semiconductor fin;

a spacer layer lining the first sidewall of the first semiconductor fin, a top surface of the STI structure, and the third sidewall of the second semiconductor fin;

an epitaxy structure having a first portion extending from a top surface of the first semiconductor fin to beyond the first sidewall of the first semiconductor fin, and a second portion extending from the top surface of the first semiconductor fin to a top end of the spacer layer, the first portion and the second portion forming an asymmetrical pattern when viewed in a cross-section taken along longitudinal axes of the first and second semiconductor fins;

a spacer layer abutting the first sidewall of the first semiconductor fin, wherein the second sidewall of the first semiconductor fin is free from coverage of the spacer layer; and

a gate stack over the substrate and crossing the first semiconductor fin and the second semiconductor fin.

11. The semiconductor of claim 10 , further comprising a dielectric material in contact with the spacer layer, wherein a top surface of the dielectric material is lower than a top surface of the semiconductor fin and a top surface of the space layer.

12. The semiconductor of claim 10 , further comprising a dielectric material in contact with the spacer layer, wherein a top surface of the dielectric material is lower than a top surface of the semiconductor fin and higher than a top surface of the space layer.

13. The semiconductor of claim 10 , wherein an interface between the epitaxy structure and the spacer layer is substantially level with a top surface of the first semiconductor fin.

14. The semiconductor of claim 10 , wherein an interface between the epitaxy structure and the spacer layer is lower than a top surface of the first semiconductor fin.

15. The semiconductor device of claim 1 , wherein the epitaxy structure is in contact with a top surface of the semiconductor fin.

16. The semiconductor device of claim 1 , further comprising a dielectric material over the fin spacer.

17. The semiconductor device of claim 16 , wherein the dielectric material is separated from the first semiconductor fin and the second semiconductor fin.

18. The semiconductor device of claim 16 , wherein the dielectric material has a linear shape cross-section.

19. The semiconductor device of claim 16 , wherein a topmost surface of the dielectric material is lower than a topmost surface of the fin spacer.

20. The semiconductor device of claim 16 , wherein a topmost surface of the dielectric material is higher than a topmost surface of the fin spacer.