IP Library › Granted Patent US 10,546,867
Granted Patent B2
US 10,546,867 · App. 15/908,006 · Granted Jan 28, 2020

Method for manufacturing semiconductor device and semiconductor device

Inventor: Yuya Matsuda (Mie, JP)
Assignee: Toshiba Memory Corporation
H01L27/11556H01L27/1157H01L27/11524H01L27/11573H01L27/11575H01L27/11582H01L21/823871H01L21/823885H01L27/11529H01L27/11534H01L27/11548
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Quick Facts
Patent No.
US 10,546,867
App. No.
15/908,006
Granted
Jan 28, 2020
Kind
B2
Abstract

According to one embodiment, a method for manufacturing a semiconductor device includes forming a first metal material inside the first holes; forming a plurality of metal layers on the first region, the metal layers being stacked with an insulator interposed, the metal layers including a plurality of terrace portions arranged in a staircase configuration with a level difference; forming a second insulating layer on the first insulating layer and on the terrace portions; simultaneously forming a second hole and a plurality of third holes piercing the second insulating layer, the second hole reaching the first metal material, the third holes reaching the terrace portions; and forming a second metal material inside the second hole and inside the third holes.

Claims (38)

1. A method for manufacturing a semiconductor device, comprising:

forming a transistor in a second region of a substrate, the substrate including a first region and the second region, the second region being at a periphery of the first region, and the transistor including an active region and a gate electrode;

forming a first insulating layer on the second region, the first insulating layer covering the transistor;

forming a plurality of first holes piercing the first insulating layer, and reaching the active region and the gate electrode;

forming a first metal material inside the first holes;

forming a plurality of metal layers on the first region, the metal layers being stacked with an insulator interposed, and the metal layers including a plurality of terrace portions arranged in a staircase configuration with a level difference;

forming a second insulating layer on the first insulating layer and on the terrace portions;

simultaneously forming a second hole and a plurality of third holes piercing the second insulating layer, the second hole reaching the first metal material inside the first holes, the first metal material being exposed at a bottom of the second hole, and the third holes reaching the terrace portions; and

forming a second metal material inside the second hole and inside the third holes, the second metal material inside the second hole being connected to the first metal material inside the first holes, and the second metal material inside the third holes being connected to the terrace portions of the metal layers.

2. The method according to claim 1 , wherein the first metal material and the metal layer include tungsten as the major component.

3. The method according to claim 1 , wherein a length of one of the first holes is shorter than a length of the second hole.

4. The method according to claim 1 , wherein a length of the first metal material is greater than a thickness of one layer of the metal layers.

5. The method according to claim 1 , wherein

a stacked body is formed on the first region, the stacked body including a plurality of first layers and a plurality of second layers, the first layers and the second layers including a first layer and a second layer stacked alternately,

the first layers form, in a portion of the stacked body, the terrace portions arranged in the staircase configuration with the level difference, and

the first layers are replaced with the metal layers after the forming of the second insulating layer on the terrace portions of the first layers.

6. A method for manufacturing a semiconductor device, comprising:

forming a transistor in a second region of a substrate, the substrate including a first region, the second region, and a third region, the second region being at a periphery of the first region, the third region being at a periphery of the second region, and the transistor including an active region and a gate electrode;

forming a first insulating layer on the second region and on the third region, the first insulating layer covering the transistor;

forming a plurality of first holes and a first trench piercing the first insulating layer, the first holes reaching the active region and the gate electrode, and the first trench reaching at least a surface of the substrate in the third region;

forming a first metal material inside the first holes;

forming a second metal material inside the first trench;

forming a plurality of metal layers on the first region, the metal layers being stacked with an insulator interposed, and the metal layers including a plurality of terrace portions arranged in a staircase configuration with a level difference;

forming a second insulating layer on the first insulating layer and on the terrace portions;

simultaneously forming a second hole, a second trench, and third holes piercing the second insulating layer, the second hole reaching the first metal material inside the first holes, the first metal material being exposed at a bottom of the second hole, the second trench reaching the second metal material, and the third holes reaching the terrace portions; and

forming a third metal material inside the second hole, inside the second trench, and inside the third holes, the third metal material inside the second hole being connected to the first metal material inside the first holes, the third metal material inside the second trench being connected to the second metal material inside the first trench, and the third metal material inside the third holes being connected to the terrace portions of the metal layers.

7. The method according to claim 6 , wherein the first metal material, the second metal material, and the metal layers include tungsten as the major component.

8. The method according to claim 6 , wherein a length of one of the first holes is shorter than a length of the second hole.

9. The method according to claim 6 , wherein a length of the first metal material is greater than a thickness of one layer of the metal layers.

10. The method according to claim 6 , wherein a depth-direction size of the first trench is smaller than a depth-direction size of the second trench.

11. The method according to claim 6 , wherein

a width of the first trench is larger than a diameter of one of the first holes, and

a width of the second trench is larger than a diameter of the second hole.

12. The method according to claim 6 , wherein the first trench and the second trench continuously surround a periphery of the second region.

13. The method according to claim 6 , wherein

a stacked body is formed on the first region, the stacked body including a plurality of first layers and a plurality of second layers, the first layers and the second layers including a first layer and a second layer stacked alternately,

the first layers form, in a portion of the stacked body, the terrace portions arranged in the staircase configuration with the level difference, and

the first layers are replaced with the metal layers after the forming of the second insulating layer on the terrace portions of the first layers.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2018
From: MATSUDA, YUYA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 045065/0587 →
Priority Claims (1)
JP 2017-163695 · Aug 28, 2017 · national
Continuity (1)
Related Publication 20190067310A1 · Feb 28, 2019
Cited By (1)
US 12,262,535