Integrated characterization vehicles for non-volatile memory cells
In example implementations, an integrated characterization vehicle is provided. The integrated characterization vehicle includes a memristor, a configuration cache and an analog measurement tile. The memristor has a driving unit to limit an amount of current that is driven through the memristor during testing. The configuration cache provides test parameters to control the testing of the memristor. The analog measurement tile provides a voltage to the memristor in accordance with the test parameters and to record a response of the memristor.
1. A circuit, comprising:
a pair of driving units coupled to a non-volatile memory device, wherein each one of the pair of driving units comprises a pair of current mirrors to limit an amount of current across the non-volatile memory device;
an N to 1 multiplexer communicatively coupled to the driving unit;
a transimpedance amplifier to convert a current from the driving unit to a voltage;
a live output coupled to the transimpedance amplifier; and
a sample and hold output coupled to the transimpedance amplifier.
2. The circuit of claim 1 , comprising:
a plurality of pairs of driving units, wherein each one of the plurality of pairs of driving units are coupled to the N to 1 multiplexer.
3. The circuit of claim 1 , wherein a first driving unit of the pair of driving units drives the amount of current in a first direction across the non-volatile memory device and a second driving unit of the pair of driving units drives the amount of current in a second direction across the non-volatile memory device, wherein the first direction is opposite the second direction.
4. The circuit of claim 1 , wherein a first current mirror of the pair of current mirrors comprises a pair of p-type metal oxide semiconductor (PMOS) transistors coupled to the memristor, wherein one side of the first current mirror has a pre-defined current limit value.
5. The circuit of claim 4 , wherein a second current mirror of the pair of current mirrors comprises a pair of n-type metal oxide semiconductor (NMOS) transistors coupled to the non-volatile memory device, wherein one side of the second current mirror has the pre-defined current limit value.
6. The circuit of claim 1 , wherein transimpedance amplifier, the live output, and the sample and hold output are deployed as an analog measurement tile in communication with the non-volatile memory device and a configuration cache that controls testing of the non-volatile memory device.