Fabrication method of a semiconductor structure by a gate cutting process with multiple sidewall spacers formation in a dummy gate opening

1. A fabrication method of a semiconductor structure, comprising:

providing a base substrate including a first region, a second region, and a third region between the first region and the second region;

forming a dummy gate structure extending from the first region to the second region and through the third region;

forming first doped source/drain regions in the base substrate on both sides of the dummy gate structure in the first region;

forming second doped source/drain regions in the base substrate on both sides of the dummy gate structure in the second region;

after forming the first doped source/drain regions and the second doped source/drain regions, forming an opening in the dummy gate structure in the third region, exposing the base substrate in the third region;

forming an interlayer dielectric layer inside the opening, wherein the interlayer dielectric layer has a top surface coplanar with the dummy gate structure; and

forming a first sidewall spacer formed on sidewalk of the opening before forming the interlayer dielectric layer and forming a second sidewall spacer on the sidewalls of the opening before forming the first sidewall spacer.

2. The fabrication method according to claim 1 , wherein the second sidewall spacer is made of a material including silicon oxide and has a thickness of about 10 angstroms to about 50 angstroms.

3. The fabrication method according to claim 1 , further including:

after forming the interlayer dielectric layer, forming a dummy gate opening by removing the dummy gate structure including a dummy gate dielectric layer and a dummy gate layer on the dummy gate dielectric layer,

wherein the second sidewall spacer is removed, when removing the dummy gate dielectric layer.

4. The fabrication method according to claim 1 , wherein:

the first region is used to form a pull-up transistor and the second region is used to form an output transistor; and

the third region is used to form the interlayer dielectric layer between gate structures of the pull-up transistor and the output transistor.

5. The fabrication method according to claim 4 , wherein the gate structure of the pull-up transistor is formed by:

removing the dummy gate structure in the first region to form a first dummy gate opening;

forming a first gate material layer in the first dummy gate opening; and

planarizing the first gate material layer to expose a surface of the interlayer dielectric layer.

6. The fabrication method according to claim 4 , wherein the gate structure of the output transistor is formed by:

removing the dummy gate structure in the second region to form a second dummy gate opening;

forming a second gate material layer in the second dummy gate opening; and

planarizing the second gate material layer to expose a surface of the interlayer dielectric layer.

7. The fabrication method according to claim 1 , wherein the base substrate includes:

a semiconductor substrate with fins protruding from the semiconductor substrate;

an isolation structure on the semiconductor substrate between the fins, wherein the isolation structure has a top surface lower than a top surface of the tins, covers a portion of sidewalls of the fins and through the dummy gate structure;

a dummy gate structure covering a portion of the sidewalls and the top surface of the fins; and

the opening exposing the top surface of the isolation structure in the third region.

8. The fabrication method according to claim 1 , wherein forming the first doped source/drain regions include:

forming first openings in the base substrate on both sides of the dummy gate structure in the first region using an etching process;

forming epitaxial layers in the first openings by a selective epitaxial deposition method;

and doping the epitaxial layers to form the first doped source/drain regions.

9. The fabrication method according to claim 1 , further including:

forming a first protecting layer on the base substrate and the dummy gate structure, in the second and third regions, before forming the first doped source/drain regions, wherein the first protecting layer has a thickness of about 6 nm to about 10 nm.

10. The fabrication method according to claim 9 , wherein forming the first protecting layer includes:

forming a first protecting film on the base substrate and the dummy gate structure, in the first, second and third regions; and

removing a portion of the first protecting film from the base substrate and the dummy gate structure, in the first region.

11. The fabrication method according to claim 1 , further including:

forming a second protecting layer on the base substrate and the dummy gate structure, in the first and third regions, before forming the second doped source/drain regions, wherein the second protecting layer has a thickness of about 6 nm to about 10 nm.

12. The fabrication method according to claim 11 , wherein forming the second protecting layer include:

forming a second protecting film on the base substrate and the dummy gate structure, in the first, second and third regions; and

removing a portion of the second protecting film from the base substrate and the dummy gate structure, in the second region.

13. The fabrication method according to claim 1 , wherein forming the second doped source/drain regions include:

forming second openings in the base substrate on both sides of the dummy gate structure in the second region using an etching process;

forming epitaxial layers in the second openings by a selective epitaxial deposition method; and

doping the epitaxial layers to form the second doped source/drain regions.

14. The fabrication method according to claim 1 , wherein a size of the opening along an extending direction of the dummy gate structure is about 20 nm to about 40 nm.

15. The fabrication method according to claim 1 , further including:

removing the dummy gate structure to form a dummy gate opening, after forming the interlayer dielectric layer.

16. The fabrication method according to claim 15 , wherein the dummy gate structure includes a dummy gate dielectric layer and a dummy gate layer on the dummy gate dielectric layer.

17. The fabrication method according to claim 1 , wherein the first sidewall spacer is made of a material including silicon nitride, and has a thickness of about 2 nm to about 3 nm.