IP Library Patent Application 15909454
Patent Application
App. No. 15/909,454

MEMORY DEVICE

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Patent No.
US None
App. No.
15/909,454
Abstract

A memory device includes a first conductive layer, a second conductive layer, and a variable resistance layer disposed between the first and second conductive layers. The variable resistance layer includes a first layer containing a semiconductor or a first metal oxide, a second layer disposed between the first layer and the first conductive layer, and containing a second metal oxide, and a first amorphous layer disposed between the second layer and the first conductive layer.

Claims (45)

1 . A memory device comprising:

a first conductive layer;

a second conductive layer; and

a variable resistance layer disposed between the first and second conductive layers, wherein

the variable resistance layer comprises:

a first layer comprising a semiconductor or a first metal oxide;

a second layer disposed between the first layer and the first conductive layer, and comprising a second metal oxide;

a first amorphous layer disposed between the second layer and the first conductive layer; and

a second amorphous layer disposed between the first layer and the second layer.

2 . The memory device according to claim 1 , wherein the first amorphous layer comprises an oxide, a nitride, or an oxynitride.

3 . The memory device according to claim 1 , wherein the first amorphous layer comprises a third metal oxide that comprises two or more metal elements.

4 . The memory device according to claim 1 , wherein the first amorphous layer has a stacked structure of two or more metal oxide films.

5 . (canceled)

6 . The memory device according to claim 1 , wherein the second amorphous layer is formed of an oxide, a nitride, or an oxynitride.

7 . The memory device according to claim 6 , wherein the second amorphous layer has a stacked structure of two or more metal oxide films selected from the group consisting of aluminum oxide, hafnium oxide, and zirconium oxide.

8 . The memory device according to claim 1 , wherein the first layer has a resistivity higher than that of the second layer.

9 . The memory device according to claim 1 , wherein the first amorphous layer comprises a third metal oxide, and a standard Gibbs energy of the third metal oxide is smaller than a standard Gibbs energy of the second metal oxide.

10 . The memory device according to claim 1 , wherein the first layer does not include atoms of the second layer.

11 . The memory device according to claim 1 , wherein the first amorphous layer is arranged to absorb oxygen from the first layer.

12 . The memory device according to claim 1 , wherein the second amorphous layer does include atoms of the first or second layers.

13 . The memory device according to claim 1 , wherein the first amorphous layer has a thickness 0.2 nm to 3 nm.

14 . The memory device according to claim 1 , wherein the memory device comprises memory cells that are three-dimensionally arranged.

15 . A memory device comprising:

a first conductive layer;

a second conductive layer; and

a variable resistance layer disposed between the first and second conductive layers, wherein

the variable resistance layer comprises:

a first layer having a first resistivity;

a second layer having a second resistivity that is higher than the first resistivity;

a first amorphous layer disposed between the first conductive layer and the second conductive layer, and

a second amorphous layer disposed between the first layer and the second layer.

16 . The memory device of claim 15 , further comprising:

wherein the first amorphous layer is disposed between the first layer and the first conductive layer.

17 . A method of making a memory device comprising:

forming a first conductive layer;

forming a second conductive layer; and

forming a variable resistance layer between the first and second conductive layers, wherein

the variable resistance layer comprises:

a first layer comprising a semiconductor or a first metal oxide;

a second layer disposed between the first layer and the first conductive layer, and comprising a second metal oxide;

a first amorphous layer disposed between the second layer and the first conductive layer; and

a second amorphous layer disposed between the first layer and the second layer.

18 . The method according to claim 17 , wherein the first amorphous layer comprises an oxide, a nitride, or an oxynitride.

19 . The method according to claim 17 , wherein the first amorphous layer comprises a third metal oxide that comprises two or more metal elements.

20 . The method according to claim 17 , wherein the first amorphous layer has a stacked structure of two or more metal oxide films.

Assignments (4)
CHANGE OF NAME Recorded Jan 17, 2022
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058670/0930 →
CHANGE OF NAME Recorded Jan 17, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058751/0266 →
MERGER Recorded Jan 17, 2022
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 058751/0995 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2018
From: YAMAMOTO, KAZUHIKO; ARAYASHIKI, YUSUKE; ISHIKAWA, KANA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 045518/0783 →