Power semiconductor device with charge balance design
A semiconductor body having first and second vertically spaced apart surfaces is formed. A gate trench that vertically extends from the first surface of the semiconductor body towards the second surface is formed. A gate electrode and a gate dielectric are formed in the gate trench. The gate dielectric electrically insulates the gate electrode from adjacent semiconductor material. A doped superjunction region vertically extending from a bottom of the gate trench towards the second surface of the semiconductor body is formed. The doped superjunction region includes first, second, and third doped pillars vertically extending from the first surface of the first semiconductor layer and directly adjoining one another. The second pillar is laterally centered between the first and third pillars and has an opposite conductivity type as the first and third pillars.
1. A vertical trenched gate transistor being formed in a semiconductor body having first and second vertically spaced apart surfaces, the vertical trenched gate transistor comprising:
a first doped semiconductor region extending from the first surface into the semiconductor body and having a first conductivity type;
a second doped semiconductor region disposed beneath the first doped semiconductor region and having a second conductivity type that is opposite from the first conductivity type;
a third doped semiconductor region disposed beneath the second doped semiconductor region, the third doped semiconductor region having the first conductivity type and having a lower doping concentration than the first doped semiconductor region;
a fourth doped semiconductor region disposed beneath the third doped semiconductor region, the fourth doped semiconductor region having the first conductivity type and having a higher doping concentration than the third doped semiconductor region;
a gate trench extending from the first surface into the semiconductor body and through the first and second semiconductor regions, the gate trench comprising an electrically conductive gate electrode and a gate dielectric that insulates the gate electrode from the semiconductor body;
a doped superjunction region disposed within the third doped semiconductor region beneath the gate trench, the doped superjunction region comprising first, second, and third doped pillars, the second pillar laterally centered between the first and third pillars and forming a p-n junction with the first and third pillars,
wherein the first and third pillars are vertically separated from the second doped semiconductor region, and
wherein the first and third pillars are laterally separated from one another by the second doped semiconductor region.
2. The vertical trenched gate transistor of claim 1 , wherein upper sides of the first and third pillars are separated from the second doped semiconductor region by a portion of the third semiconductor region.
3. The vertical trenched gate transistor of claim 1 , wherein the doped superjunction region directly adjoins only the gate trench or the third semiconductor region.
4. The vertical trenched gate transistor of claim 1 , wherein the first, second, and third doped pillars are elongated in a vertical direction that is perpendicular to the first and second surfaces of the semiconductor body.
5. The vertical trenched gate transistor of claim 1 , wherein the first doped pillar directly adjoins a first lower corner of the gate trench, and wherein the third doped pillar directly adjoins a second lower corner of the gate trench.
6. The vertical trenched gate transistor of claim 1 , wherein a bottom of the second doped pillar directly adjoins the third doped region.
7. The vertical trenched gate transistor of claim 1 , wherein a wherein a distance between a bottom of the doped superjunction region and the fourth doped semiconductor region is greater than 50% of a vertical thickness of the third doped semiconductor region.
8. The vertical trenched gate transistor of claim 7 , wherein a wherein a distance between a bottom of the doped superjunction region and the fourth doped semiconductor region is greater than 70% of a vertical thickness of the third doped semiconductor region.
9. The vertical trenched gate transistor of claim 8 , wherein a wherein a distance between a bottom of the doped superjunction region and the fourth doped semiconductor region is greater than 90% of a vertical thickness of the third doped semiconductor region.