Hybrid CMOS-MEMS devices adapted for high-temperature operation and method for their manufacture

1. Apparatus comprising a high-temperature-capable MOS component monolithically integrated with a post-MOS component comprising a suspended piezoelectric aluminum nitride member, wherein:

(a) the MOS component comprises:

an MOS integrated circuit formed in a high-temperature-capable substrate, wherein the MOS integrated circuit has one or more levels of refractory metal conductors isolated by an MOS passivation layer of dielectric material;

(b) the post-MOS component comprises:

a structural layer;

a bottom electrode directly overlying the structural layer, wherein the bottom electrode comprises doped silicon carbide, titanium, a titanium/platinum bilayer, a titanium/molybdenum bilayer, or a titanium/titanium nitride bilayer;

a layer of piezoelectric aluminum nitride directly overlying the bottom electrode;

a top electrode directly overlying the layer of piezoelectric aluminum nitride; and

a cavity underlying at least a portion of the piezoelectric aluminum nitride layer, whereby the at least a portion of the piezoelectric aluminum nitride that overlies the cavity constitutes the monolithically integrated, suspended piezoelectric aluminum nitride member;

(c) the apparatus further comprises:

a post-MOS passivation layer of silicon carbide atop the MOS passivation layer and beneath the structural layer;

at least one vertical conductor extending through the layer of piezoelectric aluminum nitride from the top electrode to the structural layer, wherein the vertical conductor has the same composition as at least part of the top electrode; and

at least one bottom-electrode via that passes through the structural layer and through the post-MOS passivation layer, wherein the bottom-electrode via connects the bottom electrode to a refractory metal conductor of the MOS integrated circuit; and

(d) the cavity is bounded from above by material of the structural layer and bounded from below by material of the post-MOS passivation layer.

2. The apparatus of claim 1 , wherein the high-temperature-capable substrate is a silicon carbide substrate.

3. The apparatus of claim 1 , wherein the structural layer comprises silicon carbide, aluminum nitride, or silicon dioxide.

4. The apparatus of claim 1 , wherein the bottom electrode comprises silicon carbide or a titanium/titanium nitride bilayer.

5. The apparatus of claim 1 , wherein the top electrode comprises silicon carbide or a titanium/titanium nitride bilayer.

6. The apparatus of claim 1 , wherein the MOS passivation layer of dielectric material comprises silicon dioxide, aluminum nitride, or silicon carbide.

7. The apparatus of claim 1 , wherein the apparatus further comprises at least one top-electrode via that passes through the structural layer and through the post-MOS passivation layer, wherein the top-electrode via connects one of the vertical conductors to a refractory metal conductor of the MOS integrated circuit.

8. The apparatus of claim 1 , wherein the bottom electrode comprises doped silicon carbide.

9. The apparatus of claim 1 , wherein the bottom electrode comprises a titanium/platinum bilayer.

10. The apparatus of claim 1 , wherein the bottom electrode comprises a titanium/titanium nitride bilayer.

11. The apparatus of claim 1 , wherein the bottom electrode comprises an amorphous conducting oxide.

12. A method for fabricating an apparatus in which a high-temperature-capable MOS integrated circuit is monolithically integrated with a MEMS device, comprising:

providing an MOS integrated circuit formed in a high-temperature-capable substrate and having one or more levels of refractory metal conductors isolated by an MOS passivation layer;

depositing a post-MOS passivation layer of silicon carbide atop the MOS passivation layer by low-pressure chemical vapor deposition (LPCVD); and

fabricating the MEMS device;

wherein fabricating the MEMS device comprises:

(a) forming a sacrificial release layer over the post-MOS passivation layer;

(b) depositing a structural layer over the post-MOS passivation layer so as to bury the sacrificial release layer;

(c) depositing a bottom electrode over the structural layer, depositing a layer of piezoelectric aluminum nitride over the bottom electrode, and depositing a top electrode over the piezoelectric aluminum nitride layer; and

(d) removing the sacrificial release layer so as to at least partially suspend the piezoelectric aluminum nitride layer;

and wherein the method further comprises:

forming vias that pass vertically through the structural layer and the post-MOS passivation layer and make electrical contact to refractory metal conductors of the MOS integrated circuit;

creating at least one hole in the piezoelectric aluminum nitride layer that extends down to the structural layer; and

filling the at least one hole with an electrical conductor concurrently with the depositing of the top electrode.

13. The method of claim 12 , wherein the sacrificial release layer is formed of polycrystalline silicon.

14. The method of claim 12 , wherein the structural layer comprises silicon carbide deposited by LPCVD.

15. The method of claim 12 , wherein the bottom electrode comprises doped silicon carbide deposited by LPCVD.

16. The method of claim 12 , wherein the bottom electrode comprises a titanium/titanium-nitride bilayer deposited by sputtering.

17. The method of claim 12 , wherein the depositing the layer of piezoelectric aluminum nitride over the bottom electrode is carried out by reactive sputter deposition.

18. The method of claim 12 , wherein the depositing the layer of piezoelectric aluminum nitride over the bottom electrode is carried out by metalorganic chemical vapor deposition.

19. The method of claim 12 , wherein the removing the sacrificial release layer comprises:

etching release trenches through the piezoelectric aluminum nitride layer and through the structural layer down to the sacrificial release layer; and

removing the sacrificial release layer by isotropic fluorine-based etching.