IP Library Granted Patent US 10,283,612
Granted Patent B2
US 10,283,612 · App. 15/911,113 · Granted May 7, 2019

Semiconductor device and manufacturing method therefor

Inventors: Chih-Ming Sun (HsinChu, TW); Hsin-Hui Hsu (HsinChu, TW); Ming-Han Tsai (HsinChu, TW)
Assignee: PIXART IMAGING INCORPORATION
H01L29/518H01L21/3086H01L21/76224H01L29/401H01L29/42324
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Quick Facts
Patent No.
US 10,283,612
App. No.
15/911,113
Granted
May 7, 2019
Kind
B2
Abstract

The present invention discloses a manufacturing method for a semiconductor device. The manufacturing method includes: providing a substrate; forming a semiconductor stacked structure on the substrate; forming at least apart of a stacked cap layer on the semiconductor stacked structure, wherein the part of the stacked cap layer includes a nitride layer; removing a part of the nitride layer; forming the rest part of the stacked cap layer; forming a protection layer on the stacked cap layer, and etching the protection layer to form an opening, wherein the nitride layer is not exposed by the opening; and introducing an etchant material into the opening to etch the substrate. The present invention also provides a semiconductor device made by the method.

Claims (23)

1. A manufacturing method for a semiconductor device, comprising the steps of:

providing a substrate;

forming a semiconductor stacked structure on the substrate;

forming a stacked cap layer on the semiconductor stacked structure, wherein the stacked cap layer includes a nitride layer;

forming a protection layer on the stacked cap layer, and etching the protection layer to form an opening, wherein at least a part of the nitride layer is exposed by the opening;

forming an oxide protection layer on a sidewall of the opening, to cover at least the exposed part of the nitride layer; and

introducing an etchant material into the opening to etch the substrate.

2. The manufacturing method for the semiconductor device of claim 1 , wherein the step of forming the semiconductor stacked structure on the substrate includes the sub-steps of:

forming a shallow trench isolation (STI) structure on the substrate; and

forming a gate structure and a spacer layer on the STI structure.

3. The manufacturing method for the semiconductor device of claim 2 , wherein the step of forming the gate structure includes the sub-steps of:

forming a first gate structure on the STI structure;

forming a nitride dielectric layer on the first gate structure;

forming an oxide dielectric layer on the nitride dielectric layer; and

forming a second gate structure on the oxide dielectric layer.

4. The manufacturing method for the semiconductor device of claim 2 , wherein the step of forming the spacer layer includes the sub-steps of:

forming an oxide spacer layer outside a sidewall of the gate structure; and

forming a nitride spacer layer outside a sidewall of the oxide spacer layer.

5. The manufacturing method for the semiconductor device of claim 2 , wherein the step of forming the stacked cap layer on the semiconductor stacked structure includes the sub-steps of:

forming a first oxide cap layer on the semiconductor stacked structure;

forming the nitride layer on the first oxide cap layer; and

forming a second oxide cap layer on the nitride layer.

6. The manufacturing method for the semiconductor device of claim 1 , wherein the etchant material includes sulfur hexafluoride (SF6) or xenon difluoride (XeF2).

Priority Claims (1)
TW 104119183 A · Jun 12, 2015 · national
Continuity (2)
Division 15068573 · Mar 12, 2016
Related Publication 20180190786A1 · Jul 5, 2018