Differential offset calibration of chopping switches in time-interleaved analog-to-digital converters
An example apparatus for analog-to-digital conversion includes a plurality of channels each including an analog-to-digital converter (ADC), a switch configured to couple a differential input to the ADC, a first offset calibration circuit coupled to an output of the ADC, a multiplier coupled to an output of the first offset calibration circuit, a second offset calibration circuit coupled to an output of the multiplier, and a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier. The apparatus further includes a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and a time-skew calibration circuit coupled to an output of the gain calibration circuit.
1. An apparatus for analog-to-digital conversion, comprising:
a plurality of channels each including:
an analog-to-digital converter (ADC);
a switch configured to couple a differential input to the ADC;
a first offset calibration circuit coupled to an output of the ADC;
a multiplier coupled to an output of the first offset calibration circuit;
a second offset calibration circuit coupled to an output of the multiplier; and
a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier;
a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and
a time-skew calibration circuit coupled to an output of the gain calibration circuit.
2. The apparatus of claim 1 , wherein the second offset calibration circuit includes a control input configured to freeze an accumulator therein.
3. The apparatus of claim 2 , further comprising:
a control circuit configured to disable the differential input at a first time, freeze the accumulator in the second offset calibration circuit at a second time after the first time, and enable the differential input after the second time.
4. The apparatus of claim 1 , wherein the time-skew calibration circuit is coupled to the PRBS generator in each of the plurality of channels.
5. The apparatus of claim 1 , wherein the switch is a chopping circuit.
6. The apparatus of claim 5 , wherein the chopping circuit is configured to alternate coupling positive and negative components of the differential input to inverting and non-inverting terminals of the ADC.
7. The apparatus of claim 6 , wherein the chopping circuit is configured to alternate coupling the positive and the negative components of the differential input to the inverting and the non-inverting terminals of the ADC based on a signal output from the PRBS generator.
8. A integrated circuit (IC), comprising:
an analog circuit configured to generate a differential signal;
analog-to-digital conversion circuitry including:
a plurality of channels each including:
an analog-to-digital converter (ADC);
a switch configured to couple a differential input to the ADC;
a first offset calibration circuit coupled to an output of the ADC;
a multiplier coupled to an output of the first offset calibration circuit;
a second offset calibration circuit coupled to an output of the multiplier; and
a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier;
a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and
a time-skew calibration circuit coupled to an output of the gain calibration circuit.
9. The IC of claim 8 , further comprising:
a digital circuit configured to receive a digital signal from the analog-to-digital conversion circuitry.
10. The IC of claim 8 , wherein the second offset calibration circuit includes a control input configured to freeze an accumulator therein.
11. The IC of claim 10 , further comprising:
a control circuit configured to disable the differential input at a first time, freeze the accumulator in the second offset calibration circuit at a second time after the first time, and enable the differential input after the second time.
12. The IC of claim 8 , wherein the time-skew calibration circuit is coupled to the PRBS generator in each of the plurality of channels.
13. The IC of claim 8 , wherein the switch is a chopping circuit.
14. The IC of claim 13 , wherein the chopping circuit is configured to alternate coupling positive and negative components of the differential input to inverting and non-inverting terminals of the ADC.
15. The IC of claim 14 , wherein the chopping circuit is configured to alternate coupling the positive and the negative components of the differential input to the inverting and the non-inverting terminals of the ADC based on a signal output from the PRBS generator.
16. A method of calibrating analog-to-digital conversion circuitry, comprising:
disabling, at a first time, a differential input to a switch configured to couple the differential input to an analog-to-digital converter (ADC);
operating a first offset calibration circuit coupled to an output of the ADC, a multiplier coupled to an output of the first calibration circuit, and a second offset calibration circuit coupled to an output of the multiplier;
disabling an accumulator in the second offset calibration circuit at a second time after the first time; and
enabling the differential input after the second time.
17. The method of claim 16 , further comprising:
providing a pseudorandom bit sequence to the switch and the multiplier.
18. The method of claim 17 , further comprising:
providing an output of the second offset calibration circuit to a gain calibration circuit;
providing an output of the gain calibration circuit to a time-skew calibration circuit; and
providing the pseudorandom bit sequence to the time-skew calibration circuit.
19. The method of claim 16 , wherein the switch is a chopping circuit.
20. The method claim 19 , wherein the chopping circuit is configured to alternate coupling positive and negative components of the differential input to inverting and non-inverting terminals of the ADC.