Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
1. A system comprising:
a system memory; and
a processor coupled to the system memory over a memory interface, the processor comprising a plurality of simultaneous multi-threading (SMT) cores coupled over an interconnect to simultaneously execute multiple threads, each of the SMT cores including a Level 1 instruction cache and a Level 1 data cache;
a Level 2 (L2) cache and a Level 3 cache shared by at least two of the cores;
at least one of the cores comprising:
an instruction fetch circuit to fetch instructions from a memory subsystem;
a decoder to decode the instructions;
a source register to store a plurality of 64-bit packed data elements;
a destination register to store a plurality of packed data elements;
execution circuitry to execute a vector leading zero count instruction to generate plurality of count values indicating a number of consecutive zeroes in each of the 64-bit packed data elements starting at a most significant bit position in each of the 64-bit packed data elements, the execution circuitry to store each count value in a packed data element location in the destination vector register corresponding to one of the 64-bit packed data elements.
2. The system of claim 1 wherein the execution circuitry further comprises:
a plurality of Arithmetic Logic Units (ALUs) a first set of one or more of the ALUs to execute a first subset of the instructions and a second set of one or more of the ALUs to execute a second subset of the instructions.
3. The system of claim 2 wherein the first set of ALUs are to process operands having different data widths and/or data formats than the second set of ALUs.
4. The system of claim 1 further comprising:
a branch prediction unit to predict a next sequence of instructions to fetch.
5. The system of claim 4 further comprising:
a prefetcher to fetch the next sequence of instructions.
6. The system of claim 1 further comprising:
a network interface to communicatively couple the processor to a network.
7. The system of claim 1 wherein the system memory comprises a double data rate (DDR) dynamic random access memory (DRAM).
8. The system of claim 1 further comprising:
a storage device coupled to at least one processor.
9. The system of claim 1 further comprising:
one or more graphics processing units (GPUs) coupled to the processors to perform graphics operations.
10. The system of claim 1 wherein the processor is one of a plurality of processors, the system further comprising:
a first interconnect to couple two or more of the plurality of processors; and
a second interconnect to couple one or more of the processors to one or more system components.
11. A system comprising:
a system memory; and
a processor coupled to the system memory over a memory interface, the processor comprising a plurality of simultaneous multi-threading (SMT) cores coupled over an interconnect to simultaneously execute multiple threads, each of the SMT cores including a Level 1 instruction cache and a Level 1 data cache;
a Level 2 (L2) cache and a Level 3 cache shared by at least two of the cores;
at least one of the cores comprising:
an instruction fetch circuit to fetch instructions from a memory subsystem;
a decoder to decode the instructions;
a source register to store a plurality of 32-bit packed data elements;
a destination register to store a plurality of packed data elements;
execution circuitry to execute a vector leading zero count instruction to generate plurality of count values indicating a number of consecutive zeroes in each of the 32-bit packed data elements starting at a most significant bit position in each of the 32-bit packed data elements, the execution circuitry to store each count value in a packed data element location in the destination vector register corresponding to one of the 32-bit packed data elements.
12. The system of claim 11 wherein the processor is one of a plurality of processors, the system further comprising:
a first interconnect to couple two or more of the plurality of processors; and
a second interconnect to couple one or more of the processors to one or more system components.