Laterally-doped MEMS resonator with piezoelectric layer
A semiconductor device includes a first silicon layer with first and second regions of substantially different dopant concentration and a resonant MEMS member formed in the first region. A piezoelectric layer is disposed over the resonant MEMS member and conductive material is disposed over the piezoelectric layer and patterned to form first and second electrodes.
1 . A semiconductor device comprising:
a first silicon layer, a second silicon layer and a third silicon layer;
the first silicon layer being disposed between the second silicon layer and the third silicon layer, the first silicon layer having first and second regions, the first and second regions being differently doped from one another;
a first microelectromechanical system (MEMS) resonant structure formed with the first region;
a second MEMS resonant structure formed with the second region;
a piezoelectric layer disposed over the resonant structure of the first silicon region; and
a conductive material disposed over the piezoelectric layer and patterned to form first and second electrodes;
wherein the first MEMS resonant structure and the second MEMS resonant structure have respective first-order temperature coefficients of frequency that differ from one another due, at least in part, to the different dopant concentrations of the first and second regions of the first silicon layer; and
wherein the first order temperature coefficient of frequency of the resonant structure formed with the second region of the first silicon layer is at least ten times greater than the first-order temperature coefficient of frequency of the resonant MEMS member with the first region of the first silicon layer.
2 . The semiconductor device of claim 1 wherein the first region of the first silicon layer has a dopant concentration of at least 1E19/cm 3 and the second region of the first silicon layer has a dopant concentration less than 1E18/cm 3 .
3 . The semiconductor device of claim 1 wherein the piezoelectric layer comprises aluminum nitride.
4 . The semiconductor device of claim 1 wherein the conductive material has a dopant concentration of at least 1E19/cm 3 .
5 . The semiconductor device of claim 1 further comprising exposed first and second electrical contacts which are electrically coupled to the first and second electrodes, respectively.
6 . The semiconductor device of claim 1 wherein the conductive material comprises doped polysilicon.
7 . The semiconductor device of claim 1 wherein one of the first silicon layer and the third silicon layer comprises a lid layer, the lid layer having one or more oxide-release vents, and wherein the semiconductor device further comprises at least one sputtered metal material that plugs the one or more oxide-release vents.
8 . The semiconductor device of claim 1 wherein the piezoelectric layer is disposed also over the second silicon region.
9 . A method of fabricating a semiconductor device, the method comprising:
providing a first silicon layer, a second silicon layer and a third silicon layer, the first silicon layer being disposed between the second silicon layer and the third silicon layer;
forming, within the first silicon layer, first and second regions, wherein forming the first and second regions comprises differently doping the first and second regions;
forming a first microelectromechanical system (MEMS) resonant structure with the first region of the first silicon layer and forming a second MEMS resonant structure with the second region of the first silicon layer;
disposing a piezoelectric layer over the resonant structure of the first silicon region; and
disposing a conductive layer over the piezoelectric layer in a pattern that forms electrically distinct first and second electrodes;
wherein the first MEMS resonant structure and the second MEMS resonant structure have respective first-order temperature coefficients of frequency that differ from one another due, at least in part, to the different doping of the first and second regions of the first silicon layer; and
wherein the first order temperature coefficient of frequency of the resonant structure formed with the second region of the first silicon layer is at least ten times greater than the first-order temperature coefficient of frequency of the resonant MEMS member with the first region of the first silicon layer.
10 . The method of claim 9 wherein differently doping the first and second regions comprises doping at least one of the first and second regions of the first silicon layer such that the first region has a dopant concentration of at least 1E19/cm 3 and the second region has a dopant concentration less than 1E18/cm 3 .
11 . The method of claim 9 wherein disposing the piezoelectric layer over the resonant structure comprises disposing aluminum nitride over the resonant structure.
12 . The method of claim 9 wherein disposing the conductive material comprises doping polysilicon to have a dopant concentration of at least 1E19/cm 3 .
13 . The method of claim 9 further comprising exposing, on a surface of the second silicon layer, first and second electrical contacts that are electrically coupled to the first and second electrodes, respectively.
14 . The method of claim 9 wherein disposing a conductive layer over the piezoelectric layer in a pattern that forms electrically distinct first and second electrodes comprises disposing doped polysilicon over the piezoelectric layer.
15 . The method of claim 9 wherein one of the first silicon layer and the third silicon layer comprises a lid layer, and wherein the method further comprises forming one or more oxide-release vents in the lid layer, removing at least one material through the lid layer via one or more oxide-release vents, and sputtering at least sputtered metal material to plug the one or more oxide-release vents.
16 . The method of claim 9 wherein the method comprises disposing the piezoelectric layer also over the second silicon region.
17 . A method of fabricating a semiconductor device, the method comprising:
providing a first silicon layer, a second silicon layer and a third silicon layer, the first silicon layer being disposed between the second silicon layer and the third silicon layer;
forming, within the first silicon layer, a first region and a second region, wherein forming comprises differently doping the first region and the second region;
forming a first microelectromechanical system (MEMS) resonant structure with the first region and forming a second MEMS resonant structure with the second region, wherein the forming of the first region and the second region, the forming of the first MEMS resonant structure and the forming of the second MEMS resonant structure are performed in a manner such that a first-order temperature coefficient of frequency (TCF) of the second MEMS resonant structure is at least ten times greater than the first-order temperature coefficient of frequency of the first MEMS resonant structure;
disposing a piezoelectric layer over the first region; and
disposing a conductive layer over the piezoelectric layer in a pattern that forms electrically distinct first and second electrodes;
wherein differently doping comprises
forming one or more trenches in the first silicon layer in a manner abutting the first region,
depositing a dopant source into the one or more trenches as well as onto a surface of the first region,
performing a thermally-anneal process to drive dopant from the dopant source into a top surface of the first region as well as into at least one lateral side of the first region, the at least one lateral side being defined by the one or more trenches.
18 . The method of claim 17 wherein disposing the piezoelectric layer over the first silicon layer comprises disposing a layer of aluminum nitride over the first region.
19 . The method of claim 17 wherein differently doping comprises doping the first region to have an n-type dopant concentration of at least 1E19/cm 3 .
20 . The method of claim 17 wherein disposing the conductive material comprises doping polysilicon to have a dopant concentration of at least 1E19/cm 3 .
21 . The method of claim 17 wherein one of the first silicon layer and the third silicon layer comprises a lid layer, and wherein the method further comprises forming one or more oxide-release vents in the lid layer, removing at least one material through the lid layer via one or more oxide-release vents, and sputtering at least sputtered metal material to plug the one or more oxide-release vents.
22 . The method of claim 17 wherein the method comprises disposing the piezoelectric layer also over the second silicon region.