Neuromorphic device having a plurality of synapses blocks

1. A neuromorphic device comprising:

a pre-synaptic neuron;

row lines extending from the pre-synaptic neuron in a first direction;

a post-synaptic neuron;

a column line extending from the post-synaptic neuron in a second direction perpendicular to the first direction; and

a plurality of synapses disposed in intersection regions between the row lines and the column line,

wherein the plurality of synapses comprises

a first synapse having a first memristor; and

a second synapse having a first selection device and a second memristor,

wherein the first synapse does not include any selection devices.

2. The neuromorphic device of claim 1 ,

wherein the row lines comprise

a first row line connected to the first synapse; and

a second row line connected to the second synapse.

3. The neuromorphic device of claim 2 , wherein:

a first electrode of the first memristor is directly electrically connected to the first row line, and

a second electrode of the first memristor is directly electrically connected to the column line.

4. The neuromorphic device of claim 2 , wherein:

a first electrode of the first selection device is directly electrically connected to the second row line,

a second electrode of the first selection device is directly electrically connected to a first electrode of the second memristor, and

a second electrode of the second memristor is directly electrically connected to the column line.

5. The neuromorphic device of claim 1 ,

wherein the first selection device comprises a bi-directional two-electrode device.

6. The neuromorphic device of claim 1 ,

wherein the first selection device comprises at least one of an Ovonic Threshold Switch (OTS), a metal-insulator transition material (MIT), a mixed ionic electronic conduction material (MIEC), a metal-insulator-metal stack (MIM) stack, or a Zener diode switch.

7. The neuromorphic device of claim 1 ,

wherein the first synapse and the second synapse are connected to the column line, in common.

8. The neuromorphic device of claim 1 ,

wherein the first selection device has a threshold voltage.

9. The neuromorphic device of claim 8 ,

wherein the second synapse is configured to be inactivated in a first operation voltage range lower than the threshold voltage, and activated in a second operation voltage higher than the threshold voltage.

10. The neuromorphic device of claim 9 ,

wherein the first synapse is configured to be activated in the first operation voltage range lower than the threshold voltage.

11. The neuromorphic device of claim 1 , further comprises a third synapse having a second selection device and a third memristor,

wherein the first selection device is configured to be turned-on at a first operation voltage, and the second selection device is configured to be turned-on at a second operation voltage,

wherein the first operation voltage is lower than the second operation voltage.

12. A neuromorphic device comprising:

a pre-synaptic neuron;

first row lines and second row lines extending in parallel from the pre-synaptic neuron in a first direction;

a post-synaptic neuron;

column lines extending from the post-synaptic neuron in a second direction at an angle to the first direction; and

synapse blocks disposed in intersection regions between the first and second row lines and the column lines,

wherein the synapse blocks comprise

a first synapse block to be activated at a first operation voltage; and

a second synapse block to be activated at a second operation voltage higher than the first operation voltage.

13. The neuromorphic device of claim 12 , wherein:

the first row lines are electrically connected to the first synapse block, and

the second row lines are electrically connected to the second synapse block.

14. The neuromorphic device of claim 13 , wherein:

the first synapse block comprises first synapses each having a first memristor, and

the second synapse block comprises second synapses each having a selection device and a second memristor.

15. The neuromorphic device of claim 14 ,

wherein the selection device comprises a bi-directional two-electrode switch configured to be turned-off at the first operation voltage and turned-on at the second operation voltage.

16. The neuromorphic device of claim 13 ,

wherein the column lines are connected to the first synapse block and the second synapse block.

17. A neuromorphic device comprising:

a pre-synaptic neuron;

a first row line and a second row line extending in parallel from the pre-synaptic neuron in a first direction;

a post-synaptic neuron;

a column line extending from the post-synaptic neuron in a second direction at an angle to the first direction;

a first synapse disposed in a first intersection region between the first row line and the column line; and

a second synapse disposed in a second intersection region between the second row line and the column line,

wherein the first synapse comprises a first memristor, and

the second synapse comprises a selection device and a second memristor,

wherein a first electrode of the first memristor is electrically connected to the first row line, and a second electrode of the first memristor is directly electrically connected to the column line,

wherein a first electrode of the selection device is electrically connected to the second row line, a second electrode of the selection device is electrically connected to a first electrode of the second memristor, and a second electrode of the second memristor is directly electrically connected to the column line.

18. The neuromorphic device of claim 17 , wherein:

the first electrode of the first memristor is directly electrically connected to the first row line.

19. The neuromorphic device of claim 17 , wherein

the first electrode of the selection device is directly electrically connected to the second row line,

and the second electrode of the selection device is directly electrically connected to the first electrode of the second memristor.

20. The neuromorphic device of claim 17 , wherein

the selection device is configured to be turned-on at a threshold voltage; and wherein

at an operation voltage lower than the threshold voltage, the first memristor is activated and the second memristor is inactivated.