Device for protection against electrostatic discharges with a distributed trigger circuit
An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.
1. An integrated circuit, comprising:
a first terminal;
a second terminal;
a MOS transistor having a source and drain coupled to the first terminal and second terminal, respectively, and further having a front gate and a back gate; and
a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an electrostatic discharge at one of the first terminal and the second terminal;
wherein the resistive-capacitive circuit comprises:
a capacitor having a first plate formed by a portion of the drain and a second plate formed by a first polysilicon line insulated from the portion of the drain by a capacitor dielectric layer, said first polysilicon line forming a resistor having a first terminal electrically coupled to the front gate and a second terminal electrically coupled to the back gate.
2. The integrated circuit of claim 1 , wherein the first polysilicon line includes a first silicide area that is electrically coupled to the front gate and a second silicide area that is electrically coupled to the back gate.
3. The integrated circuit of claim 1 , wherein the front gate is formed by a second polysilicon line having a same thickness as said first polysilicon line.
4. The integrated circuit of claim 3 , wherein the first and second polysilicon lines extend parallel to each other.
5. The integrated circuit of claim 1 , wherein the source and drain are formed in a first semiconductor layer and the back gate is formed by a doped well within a second semiconductor layer that is isolated from the first semiconductor layer by an oxide layer.
6. The integrated circuit of claim 5 , wherein the first semiconductor layer, oxide layer and second semiconductor layer are part of a silicon on insulator (SOI) substrate.
7. The integrated circuit of claim 1 , further comprising:
a third terminal; and
a capacitive coupling between the third terminal and back gate.
8. An integrated circuit, comprising:
a first terminal;
a second terminal;
a MOS transistor having a source and drain coupled to the first terminal and second terminal, respectively, and further having a front gate and a back gate; and
a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an electrostatic discharge at one of the first terminal and the second terminal;
wherein the resistive-capacitive circuit comprises:
a capacitor having a first plate formed by a portion of the source and a second plate formed by a first polysilicon line insulated from the portion of the source by a capacitor dielectric layer, said first polysilicon line forming a resistor having a first terminal electrically coupled to the front gate and a second terminal electrically coupled to the back gate.
9. The integrated circuit of claim 8 , wherein the first polysilicon line includes a first silicide area that is electrically coupled to the front gate and a second silicide area that is electrically coupled to the back gate.
10. The integrated circuit of claim 8 , wherein the front gate is formed by a second polysilicon line having a same thickness as said first polysilicon line.
11. The integrated circuit of claim 10 , wherein the first and second polysilicon lines extend parallel to each other.
12. The integrated circuit of claim 8 , wherein the source and drain are formed in a first semiconductor layer and the back gate is formed by a doped well within a second semiconductor layer that is isolated from the first semiconductor layer by an oxide layer.
13. The integrated circuit of claim 12 , wherein the first semiconductor layer, oxide layer and second semiconductor layer are part of a silicon on insulator (SOI) substrate.
14. The integrated circuit of claim 8 , further comprising:
a third terminal; and
a capacitive coupling between the third terminal and back gate.
15. An integrated circuit, comprising:
a first terminal;
a second terminal;
a MOS transistor having a source region and drain region coupled to the first terminal and second terminal, respectively, and further having a front gate and a back gate; and
an insulated conductive line extending over said drain region, said insulated conductive line having a first electrical connection to the front gate and a second electrical connection to the back gate;
wherein the insulated conductive line forms a resistive element extending between the first and second electrical connections; and
wherein a capacitive element includes a first electrode formed by said insulated conductive line and a second electrode formed by said drain region.
16. The integrated circuit of claim 15 , wherein the insulated conductive line comprises a polysilicon line insulated from the drain region by an insulating layer.
17. The integrated circuit of claim 16 , wherein the first terminal is formed by a first silicide region on the polysilicon line, and wherein the second terminal is formed by a second silicide region on the polysilicon line.
18. The integrated circuit of claim 17 , wherein the first electrode is formed by a portion of the polysilicon line between the first and second silicide regions.
19. An integrated circuit, comprising:
a first terminal;
a second terminal;
a MOS transistor having a source region and drain region coupled to the first terminal and second terminal, respectively, and further having a front gate and a back gate; and
an insulated conductive line extending over said source region, said insulated conductive line having a first electrical connection to the front gate and a second electrical connection to the back gate;
wherein the insulated conductive line forms a resistive element extending between the first and second electrical connections; and
wherein a capacitive element includes a first electrode formed by said insulated conductive line and a second electrode formed by said source region.
20. The integrated circuit of claim 19 , wherein the insulated conductive line comprises a polysilicon line insulated from the source region by an insulating layer.
21. The integrated circuit of claim 20 , wherein the first terminal is formed by a first silicide region on the polysilicon line, and wherein the second terminal is formed by a second silicide region on the polysilicon line.
22. The integrated circuit of claim 21 , wherein the first electrode is formed by a portion of the polysilicon line between the first and second silicide regions.