Analog to digital converter stage

1. A stage of an analog to digital converter, comprising:

an analog to digital converter coupled to an acquisition circuit having a first time constant; and

a plurality of circuits, each comprising an acquisition circuit having substantially the same time constant as the first time constant and a digital to analog converter for receiving a respective control signal based on a digital output of the analog to digital converter and for forming a difference signal as a difference between a sampled voltage held by the acquisition circuit and the digital to analog converter output.

2. The stage according to claim 1 , in which respective control signals to the digital to analog converters are variable.

3. The stage according to claim 1 , in which at least two outputs of the plurality of circuits are combined.

4. The stage according to claim 1 , in which the acquisition circuits of the plurality of circuits are sampling capacitor digital to analog converters.

5. The stage according to claim 1 , wherein the analog to digital converter comprises a switched capacitor array forming a first sampling digital to analog converter.

6. The stage according to claim 5 , in which each of the plurality of circuits comprise a switched capacitor array forming further sampling digital to analog converters, matched to the first sampling digital to analog converter.

7. The stage according to claim 6 , in which the sampling digital to analog converters of the plurality of circuits are formed from a plurality of unit cells.

8. The stage according to claim 1 , in which in at least one of the plurality of circuits the acquisition circuit is part of a first sampling digital to analog converter and is connected to a first sub-digital to analog converter.

9. The stage according to claim 1 , further comprising a data manipulation block for receiving the digital output of the analog to digital converter and modifying the digital output to provide respective control words to the digital to analog converters in the plurality of circuits.

10. The stage according to claim 1 , in which updates to a digital word supplied to one of the digital to analog converters of the plurality of circuits are offset in time from updates to another of the digital to analog converters of the plurality of circuits.

11. The stage according to claim 1 , further comprising at least one spare circuit arranged to be swapped with other ones of the other circuits.

12. The stage according to claim 1 , wherein the analog to digital converter comprises a flash converter.

13. The stage according to claim 1 , wherein the analog to digital converter is a pipelined analog to digital converter comprising one or more stages according to claim 1 .

14. An analog to digital converter using a plurality of slices having substantially matched sampling time constants operable together in response to an estimate of a digital word formed by an analog to digital converter comprising at least one but not all of the slices to form a residue having reduced thermal noise compared to a thermal noise of a single slice.

15. The analog to digital converter according to claim 14 , wherein the slices are formed of identical sampling digital to analog converters.

16. The analog to digital converter of claim 14 , wherein one slice is used to perform an analog to digital conversion in response to signals from a controller and remaining slices are used as slaves to form the residue.

17. A method of operating a plurality of matched digital to analog converter slices to form an analog to digital converter result and a residue, the method comprising:

operating one of the matched digital to analog converter slices to perform an analog to digital conversion; and

operating at least two of the matched digital to analog converter slices to perform a digital to analog conversion to form a difference between a sampled input and a digital approximation of the sampled input.

18. An analog to digital converter comprising:

a plurality of sampling digital to analog converter slices, where for a first capacitor an area of a capacitor plate divided by a plate separation distance in a first slice differs from that of a corresponding capacitor in a second slice by a first ratio, a width to length ratio of a transistor switch associated with the first capacitor in the first slice differs from that of a corresponding transistor in the second slice by substantially the first ratio.

19. A method of operating a plurality of matched digital to analog converter slices to form an analog to digital converter result and a residue, the method comprising:

sampling an input by matching slices having a same time constant;

driving a first one of the matching slices to perform an analog to digital conversion;

driving remaining ones of the matching slices with a result from the analog to digital conversion to generate a digital approximation of the sampled input; and

forming a residue representing a difference between the input and the digital approximation of the sampled input.

20. An apparatus to form an analog to digital converter result and a residue, the apparatus comprising:

first sampling slice for sampling an analog input;

two or more second sampling slices for sampling the analog input, wherein the first sampling slice and the two or more second sampling slices have a substantially same physical foot print on a substrate;

means for operating the first sampling slice to form a digital representation of the input;

controller means to drive the two or more second sampling slices based on the digital representation of the input to form an analog equivalent of the digital representation of the input; and

means for forming a difference between the input and the analog equivalent of the digital representation of the input.