Mitigation for FinFET technology using deep isolation

1. A semiconductor device comprising:

a P-N junction;

a first P-type FinFET;

a first N-type FinFET disposed adjacent the first P-type FinFET; and

a first isolation layer disposed in a trench and laterally separating the first N-type FinFET from the adjacent first P-type FinFET, the first isolation layer in the trench having a first width extending from the first N-type FinFET to the adjacent first P-type FinFET, the first isolation layer disposed in the trench having a first thickness and a first width;

a second isolation layer laterally disposed adjacent the first N-type FinFET, the second isolation layer separated from the first isolation layer by the first N-type FinFET, the second isolation layer having a second thickness and a second width, the first thickness is greater than 200 nm and the second thickness is less than 80 nm, and the first width greater than the second width;

a second N-type FinFET disposed adjacent the first N-type FinFET; and

the second isolation layer laterally separating the first N-type FinFET from the adjacent second N-type FinFET.

2. The semiconductor device of claim 1 , wherein the first P-type FinFET comprises:

a third isolation layer disposed on a side of the first P-type FinFET opposite the first isolation layer, the third isolation layer having a thickness of less than half of the first thickness of the first isolation layer.

3. The semiconductor device of claim 2 , wherein the first thickness of the first isolation layer is at least three times the thickness of the third isolation layer.

4. The semiconductor device of claim 1 further comprising: a second P-type FinFET disposed adjacent the first P-type FinFET; and

a third isolation layer laterally separating the first P-type FinFET from the adjacent second P-type FinFET, the third isolation layer having a thickness of less than half the first thickness of the first isolation layer.

5. The semiconductor device of claim 4 , wherein the thickness of the third isolation layer is less than 80 nm and the thickness of the first isolation layer is between 200 nm and 250 nm.

6. The semiconductor device of claim 4 , wherein the first width of the first isolation layer defined between the first P-type FinFET and the adjacent first N-type FinFET is greater than a width of the third isolation layer defined between the first P-type FinFET and the adjacent second P-type FinFET.

7. A semiconductor device comprising:

a P-N junction;

a first P-type FinFET;

a first N-type FinFET disposed adjacent the first P-type FinFET;

a second FinFET disposed adjacent one of the first P-type FinFET and first N-type FinFET, the second FinFET being of the same type as a closer of the first P-type FinFET and first N-type FinFET;

a first isolation layer disposed in a trench and laterally separating the first N-type FinFET from the adjacent the first P-type FinFET, the first isolation layer having a first thickness and a first width, the first width extending from the first N-type FinFET to the adjacent first P-type FinFET;

a second isolation layer laterally disposed adjacent the first N-type FinFET, the second isolation layer having a second thickness and a second width; and

a third isolation layer disposed adjacent the first P-type FinFET, one of the second or third isolation layer laterally separating the second FinFET from the adjacent one of the first P-type FinFET and first N-type FinFET, the first thickness at least 200 nm and the second and third thicknesses less than 80 nm, the second isolation layer having a thickness thinner than the thickness of the first isolation layer, and the first width greater than each of the second and third widths.

8. A method for forming a semiconductor device having a P-N junction, the method comprising:

etching a semiconductor substrate to form a plurality of high aspect ratio fins,

the plurality of high aspect ratio fins including a first high aspect ratio fin and a second high aspect ratio fin separated by a first high aspect ratio trench that extends from the first high aspect ratio fin to the second high aspect ratio fin, and a third high aspect ratio fin separated by a second high aspect ratio trench from the second high aspect ratio fin:

filling the first high aspect ratio trench and the second high aspect ratio trench with an insulation material;

removing a portion of the insulation material filling the first high aspect ratio trench and the second high aspect ratio trench while stopping the removal of the insulation material filling the first high aspect ratio trench to form a first isolation layer having a first thickness and a first width and a second isolation layer having a second thickness and a second width, the first thickness greater than 200 nm and the second thickness less than 80 nm, and the first width greater than the second width, wherein etching the semiconductor substrate to form the plurality of high aspect ratio fins further comprises:

forming the first high aspect ratio fin in a p-doped region of the semiconductor substrate; and

forming the second and third high aspect ratio fins in an n-doped region of the semiconductor substrate, the first and second high aspect ratio fins separated by the first high aspect ratio trench.

9. The method of claim 8 , wherein forming the first and second isolation layers further comprises:

forming the first thickness of the first isolation layer between 200 nm and 250 nm.

10. The method of claim 8 , wherein filling the first high aspect ratio trench with the insulation material comprises:

filling the first high aspect ratio trench with at least one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), and a low-k dielectric.

11. The method of claim 8 , wherein the first high aspect ratio fin is formed from silicon, silicon germanium, germanium or III-V material.