Data processing method, apparatus, and system
This application discloses a data processing method and apparatus. The method includes: distributing, by a first distribution circuit, a first bit stream to FEC encoders 1 to N in a round robin fashion, where digital signals 1 to N that are output after being encoded by the FEC encoders 1 to N are in a one-to-one correspondence with a least significant bit to a most significant bit of an input signal of a PAM circuit, a coding gain G X of an FEC encoder X is greater than a coding gain G Y of an FEC encoder Y, 1≤X<Y≤N, N≥2, and X, Y, and N are all integers. In the method, different FEC coding gains can be provided for links with different bit error rates, so that a requirement of a high-rate Ethernet for a high gain during long-distance data transmission is met, and physical-layer resources occupied by FEC are reduced.
1. A data processing method, comprising:
performing, by a forward error correction (FEC) encoding circuit included in a transmitter circuit, FEC encoding on a first bit stream to obtain a second bit stream, wherein the transmitter circuit comprises the FEC encoding circuit, a first distribution circuit, and a data processing circuit;
distributing, by the first distribution circuit included in the transmitter circuit, the second bit stream to N channels in a round robin fashion, wherein:
the N channels are represented by channels 1 to N, respectively,
the second bit stream comprises N digital signals,
the N digital signals are represented by digital signals 1 to N, respectively,
the digital signals 1 to N are transmitted to N subcircuits of the data processing circuit by using the channels 1 to N, respectively,
the N subcircuits are represented by subcircuits 1 to N, respectively,
the digital signals 1 to N are in a one-to-one correspondence with the channels 1 to N,
the channels 1 to N are in a one-to-one correspondence with the subcircuits 1 to N,
L subcircuits of the N subcircuits are L FEC encoders,
W subcircuits of the N subcircuits are W delayers, and
the L subcircuits do not intersect with the W subcircuits;
processing, by the subcircuits 1 to N, the digital signals 1 to N, respectively, to obtain N processed digital signals, wherein:
the N processed digital signals are represented by bit streams 1 to N, respectively,
the bit streams 1 to N are in a one-to-one correspondence with the digital signals 1 to N,
the L FEC encoders perform FEC encoding processing on L input digital signals, respectively, to obtain L bit streams,
the W delayers perform delay processing on W input digital signals, respectively, to obtain W bit streams,
coding gains of the subcircuits 1 to N are represented by G 1 to G N , respectively, and
a coding gain of a subcircuit X is G X , a coding gain of a subcircuit Y is G Y , G X >G Y , L+W=N, L≥1, W≥0, 1≤X<Y≤N, N≥2, and L, W, X, Y, and N are integers; and
sending, by the subcircuits 1 to N, the bit streams 1 to N to a pulse amplitude modulation (PAM) circuit, wherein the PAM circuit is configured to modulate the bit streams 1 to N, wherein the bit streams 1 to N are an input signal of the PAM circuit, and the bit streams 1 to N are in a one-to-one correspondence with a least significant bit to a most significant bit of the input signal.
2. The method according to claim 1 , wherein the subcircuit 1 is an FEC encoder, G 1 >G N , and G 1 is greater than or equal to each coding gain in G 2 to G N-1 .
3. The method according to claim 1 , wherein the transmitter circuit further comprises a first alignment marker addition circuit, and the method further comprises:
after the first distribution circuit distributes the first bit stream to the channels 1 to N in a round robin fashion, and before the subcircuits 1 to N process the digital signals 1 to N, respectively, receiving, by the first alignment marker addition circuit, the digital signals 1 to N, and adding, by the first alignment marker addition circuit, first alignment markers 1 to N to the digital signals 1 to N, wherein the digital signals 1 to N are in a one-to-one correspondence with the first alignment markers 1 to N, and the first alignment markers 1 to N are used for determining boundaries of the bit streams 1 to N; or
after the subcircuits 1 to N send the bit streams 1 to N to the pulse amplitude modulation PAM circuit, receiving, by the first alignment marker addition circuit, the bit streams 1 to N, and adding, by the first alignment marker addition circuit, first alignment markers 1 to N to the bit streams 1 to N, wherein the bit streams 1 to N are in a one-to-one correspondence with the first alignment markers 1 to N, and the first alignment markers 1 to N are used for determining boundaries of the bit streams 1 to N.
4. The method according to claim 1 , wherein the transmitter circuit further comprises a second distribution circuit, the PAM circuit comprises M modulators, and after the sending, by the subcircuits 1 to N, the bit streams 1 to N to a pulse amplitude modulation PAM circuit, the method further comprises:
receiving, by the second distribution circuit, the bit streams 1 to N;
distributing, by the second distribution circuit, the bit streams 1 to N, to obtain N×M bit streams BS 11 to BS NM , wherein a bit stream i corresponds to BS i1 to BS iM , and values of i are integers from 1 to N; and
sending, by the second distribution circuit, BS i1 to BS iM to the M modulators, wherein BS i1 to BS iM are in a one-to-one correspondence with the M modulators, the M modulators are respectively configured to modulate BS i1 to BS iM , and M is an integer greater than or equal to 2.
5. The method according to claim 1 , wherein the transmitter circuit further comprises a second distribution circuit and a multiplexing circuit, the PAM circuit comprises M modulators, and after the sending, by the subcircuits 1 to N, the bit streams 1 to N to a pulse amplitude modulation PAM circuit, the method further comprises:
receiving, by the second distribution circuit, the bit streams 1 to N;
distributing, by the second distribution circuit, the bit streams 1 to N, to obtain N×P bit streams AS 11 to AS NP , wherein a bit stream i corresponds to AS i1 to AS iP , and values of i are integers from 1 to N;
multiplexing, by the multiplexing circuit, the N×P bit streams AS 11 to AS NP into N×M bit streams BS 11 to BS NM , wherein a bit stream i corresponds to BS i1 to BS iM , and values of i are integers from 1 to N; and
sending, by the multiplexing circuit, BS i1 to BS iM to the M modulators, wherein BS i1 to BS iM are in a one-to-one correspondence with the M modulators, the M modulators are configured to modulate BS i1 to BS iM , respectively, P≥M, P is an integer multiple of M, and M is an integer greater than or equal to 2.
6. The method according to claim 4 , wherein the transmitter circuit further comprises a second alignment marker addition circuit, and after the sending, by the second distribution circuit, BS i1 to BS iM to the M modulators, the method further comprises:
receiving, by the second alignment marker addition circuit, BS 11 to BS NM ; and
adding, by the second alignment marker addition circuit, N×M second alignment markers to BS 11 to BS NM , respectively, wherein the N×M second alignment markers are represented by AM 11 to AM NM , the bit streams BS 11 to BS NM are in a one-to-one correspondence with the second alignment markers AM 11 to AM NM , and the second alignment markers AM 11 to AM NM are used for determining boundaries of the bit streams BS 11 to BS NM .
7. The method according to claim 5 , wherein the transmitter circuit further comprises a second alignment marker addition circuit, and after the sending, by the multiplexing circuit, BS i1 to BS iM to the M modulators, the method further comprises:
receiving, by the second alignment marker addition circuit, BS 11 to BS NM ; and
adding, by the second alignment marker addition circuit, N×M second alignment markers to BS 11 to BS NM , respectively, wherein the N×M second alignment markers are represented by AM 11 to AM NM , the bit streams BS 11 to BS NM are in a one-to-one correspondence with the second alignment markers AM 11 to AM NM , and the second alignment markers AM 11 to AM NM are used for determining boundaries of the bit streams BS 11 to BS NM .
8. A data processing method, comprising:
respectively receiving, by N subcircuits of a processing circuit included in a receiver circuit, N bit streams output by a pulse amplitude demodulation circuit, wherein the receiver circuit comprises the processing circuit, a first data merging circuit, and a forward error correction (FEC) decoding circuit, wherein:
the N subcircuits are represented by subcircuits 1 to N, respectively,
the N bit streams are represented by bit streams 1 to N, respectively,
the bit streams 1 to N are in a one-to-one correspondence with a least significant bit to a most significant bit of an output signal of the pulse amplitude demodulation circuit,
the subcircuits 1 to N are in a one-to-one correspondence with the bit streams 1 to N,
L subcircuits of the N subcircuits are L FEC decoders,
W subcircuits of the N subcircuits are W delayers,
the L subcircuits do not intersect with the W subcircuits,
L+W=N, L≥1, W≥0, N≥2, and
L, W, and N are integers;
respectively processing, by the subcircuits 1 to N, the bit streams 1 to N to obtain digital signals 1 to N, wherein the bit streams 1 to N are in a one-to-one correspondence with the digital signals 1 to N, the L FEC decoders perform FEC decoding on L input bit streams, respectively, to obtain L digital signals, and the W delayers perform delay processing on W input bit streams, respectively, to obtain W digital signals, wherein coding gains of the subcircuits 1 to N are represented by G 1 to G N , respectively, a coding gain of a subcircuit X is G X , a coding gain of a subcircuit Y is G Y , G X >G Y , 1≤X<Y≤N, and X and Y are integers;
sending, by the subcircuits 1 to N, the digital signals 1 to N to the first data merging circuit;
merging, by the first data merging circuit, the digital signals 1 to N into a serial first bit stream; and
performing, by the FEC decoding circuit, FEC decoding on the first bit stream, to obtain a second bit stream.
9. The method according to claim 8 , wherein the subcircuit 1 is an FEC decoder, G 1 >G N , and G 1 is greater than or equal to each coding gain in G 2 to G N−1 .
10. The method according to claim 8 , wherein the receiver circuit further comprises a first alignment marker identification circuit, and before the respectively receiving, by N subcircuits of the processing circuit, N bit streams output by a pulse amplitude demodulation circuit, the method further comprises:
identifying, by the first alignment marker identification circuit, first alignment markers 1 to N that are comprised in the bit streams 1 to N, wherein the bit streams 1 to N are in a one-to-one correspondence with the first alignment markers 1 to N; and
determining boundaries of the bit streams 1 to N based on the first alignment markers 1 to N.
11. The method according to claim 8 , wherein the pulse amplitude demodulation circuit comprises M demodulators, the receiver circuit further comprises a second data merging circuit, and before the receiving, by the N subcircuits of the processing circuit, the N bit streams output by the pulse amplitude demodulation circuit, the method further comprises:
receiving, by the second data merging circuit, N×M bit streams output by the M demodulators, wherein the N×M bit streams are represented by BS 11 to BS NM , respectively, a bit stream i corresponds to BS i1 to BS iM , and values of i are all integers from 1 to N; and
merging, by the second data merging circuit, BS i1 to BS iM into the bit stream i, wherein BS i1 to BS iM are in a one-to-one correspondence with the M demodulators, and M is an integer greater than or equal to 2.
12. The method according to claim 8 , wherein the pulse amplitude demodulation circuit comprises M demodulators, the receiver circuit further comprises a demultiplexing circuit and a second data merging circuit, and before the respectively receiving, by the N subcircuits of the processing circuit, the N bit streams output by the pulse amplitude demodulation circuit, the method further comprises:
receiving, by the demultiplexing circuit, N×M bit streams output by the M demodulators, wherein the N×M bit streams are represented by BS 11 to BS NM , respectively, and demultiplexing BS 11 to BS NM into N×P bit streams, wherein the N×P bit streams are represented by AS 11 to AS NP , respectively, a bit stream i corresponds to BS i1 to BS iM , values of i are integers from 1 to N, the bit streams BS i1 to BS iM are in a one-to-one correspondence with the M demodulators, and M is an integer greater than or equal to 2;
receiving, by the second data merging circuit, AS 11 to AS NP ; and
merging, by the second data merging circuit, AS i1 to AS iP into the bit stream i, wherein the bit stream i corresponds to AS i1 to AS iP , values of i are all integers from 1 to N, P≥M, P is an integer multiple of M, and M is an integer greater than or equal to 2.
13. The method according to claim 11 , wherein the receiver circuit further comprises a second alignment marker identification circuit, and before the receiving, by the N subcircuits of the processing circuit, the N bit streams output by the pulse amplitude demodulation circuit, the method further comprises:
identifying, by the second alignment marker identification circuit, N×M second alignment markers comprised in BS 11 to BS NM , wherein the N×M second alignment markers are represented by AM 11 to AM NM , respectively, and BS 11 to BS NM are in a one-to-one correspondence with AM 11 to AM NM ; and
determining a boundary of each bit stream in BS 11 to BS NM based on AM 11 to AM NM .
14. A data processing apparatus, comprising:
a forward error correction (FEC) encoding circuit;
a first distribution circuit; and
a data processing circuit, wherein:
the FEC encoding circuit is configured to perform FEC encoding on a first bit stream to obtain a second bit stream;
the first distribution circuit is configured to distribute the second bit stream to N channels in a round robin fashion, wherein:
the N channels are represented by channels 1 to N, respectively,
the second bit stream comprises N digital signals,
the N digital signals are represented by digital signals 1 to N, respectively,
the digital signals 1 to N are transmitted to N subcircuits of the data processing circuit by using the channels 1 to N, respectively,
the N subcircuits are represented by subcircuits 1 to N, respectively,
the digital signals 1 to N are in a one-to-one correspondence with the channels 1 to N,
the channels 1 to N are in a one-to-one correspondence with the subcircuits 1 to N,
L subcircuits of the N subcircuits are L FEC encoders,
W subcircuits of the N subcircuits are W delayers, and
the L FEC encoders do not intersect with the W delayers;
the data processing circuit is configured to process the digital signals 1 to N by using the subcircuits 1 to N, respectively, to obtain N processed digital signals, wherein the N processed digital signals are represented by bit streams 1 to N, respectively, and the bit streams 1 to N are in a one-to-one correspondence with the digital signals 1 to N, wherein the L FEC encoders perform FEC encoding processing on L input digital signals, respectively, to obtain L bit streams, and the W delayers perform delay processing on W input digital signals, respectively, to obtain W bit streams, wherein coding gains of the subcircuits 1 to N are represented by G 1 to GA N , respectively, a coding gain of a subcircuit X is G X , a coding gain of a subcircuit Y is G Y , G X >G Y , L+W=N, L≥1, W≥0, 1≤X<Y≤N, N≥2, and L, W, X, Y, and N are integers; and
the data processing circuit is further configured to send the bit streams 1 to N to a pulse amplitude modulation (PAM) circuit, wherein the PAM circuit is configured to modulate the bit streams 1 to N, the bit streams 1 to N are an input signal of the PAM circuit, and the bit streams 1 to N are in a one-to-one correspondence with a least significant bit to a most significant bit of the input signal.
15. The data processing apparatus according to claim 14 , wherein G 1 >G N , and G 1 is greater than or equal to each coding gain in G 2 to G N−1 .
16. The data processing apparatus according to claim 14 , wherein the data processing apparatus further comprises a first alignment marker addition circuit, wherein:
the first alignment marker addition circuit is configured to: after the first distribution circuit distributes the second bit stream to the channels 1 to N in a round robin fashion, and before the subcircuits 1 to N process the digital signals 1 to N, receive the digital signals 1 to N, and add first alignment markers 1 to N to the digital signals 1 to N, wherein the digital signals 1 to N are in a one-to-one correspondence with the first alignment markers 1 to N, and the first alignment markers 1 to N are used for determining boundaries of the bit streams 1 to N; or
the first alignment marker addition circuit is configured to: after the subcircuits 1 to N send the bit streams 1 to N to the pulse amplitude modulation PAM circuit, receive the bit streams 1 to N, and add first alignment markers 1 to N to the bit streams 1 to N, wherein the bit streams 1 to N are in a one-to-one correspondence with the first alignment markers 1 to N, and the first alignment markers 1 to N are used for determining boundaries of the bit streams 1 to N.
17. The data processing apparatus according to claim 14 , wherein the PAM circuit comprises M modulators, and the data processing apparatus further comprises a second distribution circuit, wherein:
the second distribution circuit is configured to: after the subcircuits 1 to N send the bit streams 1 to N to the PAM circuit, receive the bit streams 1 to N, and distribute the bit streams 1 to N, to obtain N×M bit streams BS 11 to BS NM , wherein a bit stream i corresponds to BS i1 to BS iM , and values of i are integers from 1 to N; and
the second distribution circuit is further configured to send BS i1 to BS iM to the M modulators, wherein BS i1 to BS iM are in a one-to-one correspondence with the M modulators, the M modulators are configured to modulate BS i1 to BS iM , respectively, and M is an integer greater than or equal to 2.
18. The data processing apparatus according to claim 14 , wherein the PAM circuit comprises M modulators, and the data processing apparatus further comprises a second distribution circuit and a multiplexing circuit, wherein:
the second distribution circuit is configured to: after the subcircuits 1 to N send the bit streams 1 to N to the PAM circuit, receive the bit streams 1 to N, and distribute the bit streams 1 to N, to obtain N×P bit streams AS 11 to AS NP , wherein a bit stream i corresponds to AS il to AS iP , and values of i are integers from 1 to N;
the multiplexing circuit is configured to multiplex the N×P bit streams AS 11 to AS NP into N×M bit streams BS 11 to BS NM , wherein a bit stream i corresponds to BS i1 to BS iM , and values of i are all integers from 1 to N; and
the multiplexing circuit is further configured to send BS i1 to BS iM to the M modulators, wherein BS i1 to BS iM are in a one-to-one correspondence with the M modulators, the M modulators are configured to modulate BS i1 to BS iM , respectively, P≥M, P is an integer multiple of M, and M is an integer greater than or equal to 2.
19. The data processing apparatus according to claim 17 , wherein the data processing apparatus further comprises a second alignment marker addition circuit, wherein:
the second alignment marker addition circuit is configured to receive BS 11 to BS NM after the second distribution circuit sends BS i1 to BS iM to the M modulators; and
the second alignment marker addition circuit is further configured to add N×M second alignment markers to BS 11 to BS NM , respectively, wherein the N×M second alignment markers are represented by AM 11 to AM NM , the bit streams BS 11 to BS NM are in a one-to-one correspondence with the second alignment markers AM 11 to AM NM , and the second alignment markers AM 11 to AM NM are used for determining boundaries of the bit streams BS 11 to BS NM .
20. The data processing apparatus according to claim 18 , wherein the data processing apparatus further comprises a second alignment marker addition circuit, wherein:
the second alignment marker addition circuit is configured to receive BS 11 to BS NM after the multiplexing circuit sends BS i1 to BS iM to the M modulators; and
the second alignment marker addition circuit is further configured to add N×M second alignment markers to BS 11 to BS NM , respectively, wherein the N×M second alignment markers are represented by AM 11 to AM NM , the bit streams BS 11 to BS NM are in a one-to-one correspondence with the second alignment markers AM 11 to AM NM , and the second alignment markers AM 11 to AM NM are used for determining boundaries of the bit streams BS 11 to BS NM .
21. A data processing apparatus, comprising:
a processing circuit comprising N subcircuits;
a first data merging circuit; and
a forward error correction (FEC) decoding circuit, wherein:
the processing circuit is configured to respectively receive, by using the N subcircuits, N bit streams output by a pulse amplitude demodulation circuit, wherein:
the N subcircuits are represented by subcircuits 1 to N, respectively,
the N bit streams are represented by bit streams 1 to N, respectively,
the bit streams 1 to N are in a one-to-one correspondence with a least significant bit to a most significant bit of an output signal of the pulse amplitude demodulation circuit,
the subcircuits 1 to N are in a one-to-one correspondence with the bit streams 1 to N,
L subcircuits of the N subcircuits are L FEC decoders,
W subcircuits of the N subcircuits are W delayers,
the L FEC decoders do not intersect with the W delayers,
L+W=N, L≥1, W≥0, N≥2, and
L, W, and N are integers;
the processing circuit is further configured to respectively process the bit streams 1 to N by using the subcircuits 1 to N, to obtain digital signals 1 to N, wherein the bit streams 1 to N are in a one-to-one correspondence with the digital signals 1 to N, the L FEC decoders perform FEC decoding on L input bit streams, respectively, to obtain L digital signals, and the W delayers perform delay processing on W input bit streams, respectively, to obtain W digital signals, wherein coding gains of the subcircuits 1 to N are represented by G 1 to G N , respectively, a coding gain of a subcircuit X is G X , a coding gain of a subcircuit Y is G Y , G X >G Y , 1≤X<Y≤N, and X and Y are integers;
the subcircuits 1 to N send the digital signals 1 to N to the first data merging circuit;
the first data merging circuit is configured to merge the digital signals 1 to N into a serial first bit stream; and
the FEC decoding circuit is configured to perform FEC decoding on the first bit stream, to obtain a second bit stream.
22. The data processing apparatus according to claim 21 , wherein G 1 >G N , and G 1 is greater than or equal to each coding gain in G 2 to G N−1 .
23. The data processing apparatus according to claim 21 , wherein the data processing apparatus further comprises a first alignment marker identification circuit, wherein the first alignment marker identification circuit is configured to:
before the N subcircuits of the processing circuit receive the N bit streams output by the pulse amplitude demodulation circuit, identify first alignment markers 1 to N that are comprised in the bit streams 1 to N, wherein the bit streams 1 to N are in a one-to-one correspondence with the first alignment markers 1 to N; and
determine boundaries of the bit streams 1 to N based on the first alignment markers 1 to N.
24. The data processing apparatus according to claim 21 , wherein the pulse amplitude demodulation circuit comprises M demodulators, and the data processing apparatus further comprises a second data merging circuit, wherein the second data merging circuit is configured to:
before the N subcircuits of the processing circuit respectively receive the N bit streams output by the pulse amplitude demodulation circuit, receive N×M bit streams output by the M demodulators, wherein the N×M bit streams are represented by BS 11 to BS NM , respectively, a bit stream i corresponds to BS i1 to BS iM , and values of i are all integers from 1 to N; and
merge BS i1 to BS iM into the bit stream i, wherein BS i1 to BS iM are in a one-to-one correspondence with the M demodulators, and M is an integer greater than or equal to 2.
25. The data processing apparatus according to claim 21 , wherein the pulse amplitude demodulation circuit comprises M demodulators, and the data processing apparatus further comprises a demultiplexing circuit and the second data merging circuit, wherein:
the demultiplexing circuit is configured to: before the N subcircuits of the processing circuit receive the N bit streams output by the pulse amplitude demodulation circuit, receive N×M bit streams output by the M demodulators, wherein the N×M bit streams are represented by BS 11 to BS NM , respectively, and demultiplex BS 11 to BS NM into N×P bit streams, wherein the N×P bit streams are represented by AS 11 to AS NP , respectively, a bit stream i corresponds to BS i1 to BS iM , values of i are integers from 1 to N, the bit streams BS i1 to BS iM are in a one-to-one correspondence with the M demodulators, and M is an integer greater than or equal to 2;
the second data merging circuit is configured to receive AS 11 to AS NP ; and
the second data merging circuit is further configured to merge AS i1 to AS iP into the bit stream i, wherein the bit stream i corresponds to AS i1 to AS iP , values of i are integers from 1to N, P≥M, P is an integer multiple of M, and M is an integer greater than or equal to 2.
26. The data processing apparatus according to claim 24 , wherein the data processing apparatus further comprises a second alignment marker identification circuit, wherein the second alignment marker identification circuit is configured to:
before the N subcircuits of the processing circuit receive the N bit streams output by the pulse amplitude demodulation circuit, identify N×M second alignment markers comprised in BS 11 to BS NM , wherein the N×M second alignment markers are represented by AM 11 to AM NM , respectively, and BS 11 to BS NM are in a one-to-one correspondence with AM 11 to AM NM ; and
determine a boundary of each bit stream of BS 11 to BS NM based on AM 11 to AM NM .