Memory device, memory system, method of operating memory device, and method of operating memory system
View Patent ↗A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.
1. A method of operating a memory device including a first block and a second block, the method comprising:
applying a first pre-programming voltage to a first word line of the first block arranged on a substrate;
applying a second pre-programming voltage to a second word line of the second block vertically arranged above the first block; and
performing an erase operation on the first block or the second block,
wherein a first voltage level of the first pre-programming voltage is lower than a second voltage level of the second pre-programming voltage,
wherein each of the first and second blocks includes a plurality of NAND strings,
wherein each NAND string includes a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on the substrate, and
wherein when a program/erase cycle count is equal to or greater than a threshold value, the first and second voltage levels are towered.
2. The method of claim 1 , wherein a first application duration of the first pre-programming voltage is shorter than a second duration of the second pre-programming voltage.
3. The method of claim 2 , wherein when a program/erase cycle count is equal to or greater than a threshold value, the first application duration and the second application duration are shortened.
4. The method of claim 3 , wherein a first amount the first application duration is changed is larger than a second amount the second application duration is changed.
5. The method of claim 1 , wherein a first amount the first voltage level is changed is larger than a second amount the second voltage level is changed.
6. The method of claim 1 , wherein the first block is connected to ground selection lines under the first word line, and a common source line under the ground selection lines, and
wherein the second block is connected to string selection lines above the second word line, and bit lines above the string selection lines.
7. The method of claim 1 , the applying the first pre-programming voltage is performed when the program/erase cycle count is less than a threshold value.
8. A method of operating a memory device including a first block and a second block, the method comprising:
applying a first pre-programming voltage to a first word line of the first block arranged on a substrate when a program/erase cycle count is less than a threshold value;
applying a second pre-programming voltage to a second word line of the second block vertically arranged above the first block; and
performing an erase operation on the first block or the second block,
wherein voltage levels or application durations of the first and second pre-programming voltages are different from each other,
wherein each of the first and second blocks includes a plurality of NAND strings,
wherein each NAND string includes a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on the substrate, and
wherein when the program/erase cycle count is equal to or greater than the threshold value, the voltage levels are lowered, or the application durations are shortened.
9. The method of claim 8 , wherein when the program/erase cycle count is equal to or greater than the threshold value, the applying the first pre-programming voltage is skipped.
10. The method of claim 8 , wherein a first voltage level of the first pre-programming voltage is lower than a second voltage level of the second pre-programming voltage.
11. The method of claim 8 , wherein a first application duration of the first pre-programming voltage is shorter than a second duration of the second pre-programming voltage.
12. The method of claim 8 , wherein the first block is connected to ground selection lines under the first word line, and a common source line under the ground selection lines, and
wherein the second block is connected to string selection lines above the second word line, and bit lines above the string selection lines.
13. A method of operating a memory device including a first block and a second block, the method comprising:
applying a first pre-programming voltage to a first word line of the first block arranged on a substrate;
applying a second pre-programming voltage to a second word line of the second block vertically arranged above the first block; and
performing an erase operation on the first block or the second block,
wherein a first application duration of the first pre-programming voltage is shorter than a second duration of the second pre-programming voltage,
wherein each of the first and second blocks includes a plurality of NAND strings,
wherein each NAND string includes a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on the substrate, and
wherein when a program/erase cycle count is equal to or greater than a threshold value, the first application duration and the second application duration are shortened.
14. The method of claim 13 , wherein an application start time of the first pre-programming voltage is the same as an application start time of the second pre-programming voltage, and
wherein an application end time of the first pre-programming voltage is earlier than an application end time of the second pre-programming voltage.
15. The method of claim 13 , wherein an application end time of the first pre-programming voltage is the same as an application end time of the second pre-programming voltage, and
wherein an application start time of the first pre-programming voltage is later than an application start time of the second pre-programming voltage.
16. The method of claim 13 , further comprising: after the applying the first pre-programming voltage, applying a pass voltage lower than the first pre-programming voltage to the first word line.
17. The method of claim 13 , further comprising: after the applying the second pre-programming voltage, applying a pass voltage lower than the second pre-programming voltage to the second word line.
18. The method of claim 13 , wherein a first voltage level of the first pre-programming voltage is lower than a second voltage level of the second pre-programming voltage.
19. The method of claim 13 , wherein the first block is connected to ground selection lines under the first word line, and a common source line under the ground selection lines, and
wherein the second block is connected to string selection lines above the second word line, and bit lines above the string selection lines.