Three-dimensional vertical one-time-programmable memory comprising multiple antifuse sub-layers
View Patent ↗The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTP V ). It comprises horizontal address lines and memory holes there-through, an antifuse layer and vertical address lines in said memory holes. The antifuse layer comprises at least first and second sub-layers with different antifuse materials. The 3D-OTP V comprises no separate diode layer.
1. A three-dimensional vertical one-time-programmable memory (3D-OTP V ), comprising:
a semiconductor substrate comprising a substrate circuit;
a plurality of vertically stacked horizontal address lines above said semiconductor circuit, wherein said horizontal address lines comprise at least a first conductive material;
a plurality of memory holes through said horizontal address lines;
an antifuse layer on the sidewalls of said memory holes, said antifuse layer comprising at least first and second sub-layers, wherein said first and second sub-layers comprise different antifuse materials;
a plurality of vertical address lines in said memory holes and in contact with said anitfuse layer, wherein said vertical address lines comprise at least a second conductive material;
a plurality of OTP cells at the intersections of said horizontal and vertical address lines, wherein each of said OTP cells comprises at least a first portion of a first selected one of said horizontal address lines, at least a second portion of a second selected one of said vertical address lines, and at least a third portion of said antifuse layer;
wherein said horizontal and vertical address lines are separated by said antifuse layer only.
2. The 3D-OTP V according to claim 1 , wherein said first sub-layer comprises at least a metal oxide or silicon oxide, and second sub-layer comprise at least a metal nitride or silicon nitride.
3. The 3D-OTP V according to claim 1 , further comprising:
a first interface between said first sub-layer and selected one of said horizontal address lines;
a second interface between said second sub-layer and selected one of said vertical address lines;
wherein said first and second interfaces are different.
4. The 3D-OTP V according to claim 1 , wherein said first and second conductive materials are different conductive materials.
5. The 3D-OTP V according to claim 1 , wherein said horizontal address line, said antifuse layer and said vertical address line form a built-in diode.
6. The 3D-OTP V according to claim 5 , wherein the resistance of said diode is substantially lower than when the applied voltage has a magnitude smaller than or a polarity opposite to that of the read voltage.
7. The 3D-OTP V according to claim 6 , wherein all OTP cells coupled to a selected horizontal address line are read out in a single read cycle.
8. The 3D-OTP V according to claim 7 , wherein the I-V characteristics of said built-in diode satisfies |(V R )>>n*I(−V T ), where V R is the read voltage on said selected horizontal address line; V T is the toggle voltage of a selected vertical address line; n is the number of OTP cells on said selected horizontal address line.
9. The 3D-OTP V according to claim 1 , wherein said OTP cells form an OTP string.
10. The 3D-OTP V according to claim 9 , further comprising a vertical transistor coupled to said OTP string.
11. The 3D-OTP V according to claim 10 , wherein said vertical transistor is formed in a first portion of said memory hole, and said OTP string is formed in a second portion of said memory hole.