Low-power receiver for FSK back-channel embedded in 5.8GHz Wi-Fi OFDM packets
An ultra-low power back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8 GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the third harmonic of the local oscillator for power efficiency. The LP-65 nm CMOS receiver consumes 335 μW with a sensitivity of −72 dBm at a BER of 10 −3 and data-rate of 31.25 kb/s. The radio uses a balun and a 250 kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the local oscillator and the frequency-locked loop circuits.
1. A low power RF receiver, comprising:
an analog front-end circuit configured to receive an RF input signal and mixes the RF input signal with a front-end mixing signal to yield a down converted signal while simultaneously suppressing signals at a frequency of the front-end mixing signal, where the front-end mixing signal has a frequency set at third harmonics of a difference between frequency of the RF input signal and a target frequency for the down converted signal;
an intermediate frequency stage circuit configured to receive the down converted signal from the analog front-end circuit and routes the down converted signal into each of two circuit detection paths, where each circuit detection path further down converts the down converted signal into a baseband signal and thereby forms a pair of baseband signals; and
a baseband frequency stage circuit configured to receive the pair of baseband signals from the intermediate frequency stage circuit and demodulate bits encoded on the baseband signals, where the bits are encoded on the baseband signals using frequency-shift keying.
2. The low power RF receiver of claim 1 further comprises an antenna configured to receive the RF input signal and a balun interposed between the antenna and the analog front-end circuit.
3. The low power RF receiver of claim 1 wherein the analog front-end circuit includes a passive mixer in series with at least one amplifier.
4. The low power RF receiver of claim 1 wherein the two circuit detection paths are formed by a first circuit detection path and a second circuit detection path,
the first circuit detection path having a first mixer in series with a first low pass filter, wherein first mixer mixes the down converted signal with a first mixing signal to yield a first mixed signal, the first mixing signal having a frequency equal to a mark frequency of the binary frequency-shift keying method;
the second circuit detection path having a second mixer in series with a second low pass filter, wherein second mixer mixes the down converted signal with a second mixing signal to yield a second mixed signal, the second mixing signal has a frequency equal to a space frequency of the binary frequency-shift keying method.
5. The low power RF receiver of claim 4 wherein cutoff of the first low pass filter and cutoff of the second low pass filter are set in between zero and the space frequency of the binary frequency-shift keying method.
6. The low power RF receiver of claim 5 wherein the baseband frequency stage circuit includes an envelope detector circuit, an integrator circuit and a comparator circuit.
7. The low power RF receiver of claim 6 wherein the comparator circuit compares magnitude of signal energy in the first circuit detection path to magnitude of signal energy in the second circuit detection path and outputs a bit decision in accordance with the comparison.
8. The low power RF receiver of claim 4 further comprises a frequency-locked loop circuit interfaced with the analog front-end circuit and an intermediate frequency stage circuit, wherein the frequency-locked loop circuit generates the front-end mixing signal, the first mixing signal and the second mixing signal.
9. The low power RF receiver of claim 1 wherein the analog front-end circuit, the intermediate frequency stage circuit, and the baseband frequency stage circuit form an integrated circuit.
10. A low power RF receiver, comprising:
an analog front-end circuit configured to receive an RF input signal and operates to down convert the RF input signal to a down converted signal, where the RF input signal is encoded with a binary frequency-shift keying method; and
an intermediate frequency stage circuit configured to receive the down converted signal from the analog front-end circuit and route the down converted signal into two circuit detection paths, each circuit detection path further down converts the down converted signal into a baseband signal and thereby forms a pair of baseband signals;
a first circuit detection path having a first mixer in series with a first low pass filter, wherein first mixer mixes the down converted signal with a first mixing signal to yield a first mixed signal, the first mixing signal having a frequency equal to a mark frequency of the binary frequency-shift keying method;
a second circuit detection path having a second mixer in series with a second low pass filter, wherein second mixer mixes the down converted signal with a second mixing signal to yield a second mixed signal, the second mixing signal has a frequency equal to a space frequency of the binary frequency-shift keying method; wherein cutoff of the first low pass filter and cutoff of the second low pass filter are set in between zero and the space frequency of the binary frequency-shift keying method.
11. The low power RF receiver of claim 10 wherein the analog front-end circuit mixes the RF input signal with a front-end mixing signal, such that the front-end mixing signal has a frequency set at third harmonic of a difference between frequency of the RF input signal and a target frequency of a down converted signal.
12. The low power RF receiver of claim 10 further comprises an antenna configured to receive the RF input signal and a balun interposed between the antenna and the analog front-end circuit.
13. The low power RF receiver of claim 10 wherein the cutoff of the first low pass filter is same as the cutoff of the second low pass filter.
14. The low power RF receiver of claim 10 further comprises a baseband frequency stage circuit configured to receive the pair of baseband signals from the intermediate frequency stage circuit and demodulate bits encoded on the baseband signals, where the bits are encoded on the baseband signals using frequency-shift keying.
15. The low power RF receiver of claim 14 wherein the baseband frequency stage circuit includes an envelope detector circuit, an integrator circuit and a comparator circuit.
16. The low power RF receiver of claim 15 wherein the comparator circuit compares magnitude of signal energy in the first circuit detection path to magnitude of signal energy in the second circuit detection path and outputs a bit decision in accordance with the comparison.
17. The low power RF receiver of claim 16 further comprises a frequency-locked loop circuit interfaced with the analog front-end circuit and an intermediate frequency stage circuit, wherein the frequency-locked loop circuit generates the front-end mixing signal, the first mixing signal and the second mixing signal.
18. The low power RF receiver of claim 10 wherein the analog front-end circuit, the intermediate frequency stage circuit, and the baseband frequency stage circuit form an integrated circuit.