Configurable computing array based on three-dimensional printed memory
The present invention discloses a configurable computing array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a basic function in a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the basic functions in the math library.
1. A configurable computing array, comprising:
an array of configurable computing elements comprising at least a configurable computing element, wherein said configurable computing element comprises at least first and second three-dimensional printed memory (3D-P) arrays, said first 3D-P array storing at least a first portion of a first look-up table (LUT) for a first math function, said second 3D-P array storing at least a second portion of a second LUT for a second math function;
an array of configurable logic elements comprising at least a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library;
a plurality of configurable interconnects coupling said array of configurable computing elements and said array of configurable logic elements;
wherein said configurable computing array realizes a math function by programming said array of configurable computing elements, said array of configurable logic elements and said plurality of configurable interconnects.
2. The configurable computing array according to claim 1 , wherein said first and second 3D-P arrays are placed side-by-side on a semiconductor substrate.
3. The configurable computing array according to claim 1 , wherein said second 3D-P array is stack above said first 3D-P array.
4. The configurable computing array according to claim 3 , wherein said second 3D-P array at least partially covers said first 3D-P array.
5. The configurable computing array according to claim 1 , wherein data are recorded into said 3D-P using a printing method during manufacturing.
6. The configurable computing array according to claim 1 , wherein said first or second 3D-P array is stack above at least a selected one of said configurable logic elements.
7. The configurable computing array according to claim 6 , wherein said first or second 3D-P array at least partially covers said selected one of said configurable logic elements.
8. The configurable computing array according to claim 1 , wherein said first or second 3D-P array is stack above at least a selected one of said configurable interconnects.
9. The configurable computing array according to claim 8 , wherein said first or second 3D-P array at least partially covers said selected one of said configurable interconnects.