High density antifuse co-integrated with vertical FET
A semiconductor device including an anti-fuse is disclosed. The semiconductor anti-fuse includes a highly doped source of a first conductivity type overlying a substrate. The semiconductor anti-fuse further includes a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate. The semiconductor anti-fuse further includes a highly doped fuse region extending over the highly doped source and including an epitaxial growth, the highly doped fuse region implanted with ions.
1. A semiconductor device comprising a vertical transistor co-integrated with an anti-fuse, comprising:
a highly doped source of a first conductivity type overlying a substrate;
a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate;
a first channel region extending over the highly doped source and comprising an epitaxial growth, the first channel region located at a first location on the substrate and having a first width;
a drain comprising an epitaxial growth arranged on the channel region, the channel region extending from the highly doped source to the drain; and
a highly doped fuse region extending over the highly doped source and comprising an epitaxial growth, the highly doped fuse region located at a second location on the substrate and having a second width that is larger than the first width.
2. The semiconductor device of claim 1 , wherein the highly doped fuse region is implanted with ions.
3. The semiconductor device of claim 1 , further comprising a gate stack overlying the highly doped fuse region, comprising:
a high-k dielectric material layer;
a work function metal layer overlying the high-k dielectric material layer; and
a metal gate material overlying the work function metal layer.
4. The semiconductor device of claim 3 , further comprising a first metal contact extending partially through the high-k dielectric material.
5. The semiconductor device of claim 3 , further comprising an interlayer dielectric (ILD) layer overlying the gate stack.
6. The semiconductor device of claim 1 , further comprising:
a bottom spacer overlying the highly doped source excepting the first channel region and the highly doped fuse region.
7. The semiconductor device of claim 1 , further comprising a second metal contact extending partially through the highly doped source.
8. The semiconductor device of claim 1 , further comprising:
a bottom spacer overlying the highly doped source excepting the first channel region and the highly doped fuse region.
9. A semiconductor anti-fuse, comprising:
a highly doped source of a first conductivity type overlying a substrate;
a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate; and
a highly doped fuse region extending over the highly doped source and comprising an epitaxial growth, the highly doped fuse region implanted with ions.
10. The semiconductor anti-fuse of claim 9 , further comprising a gate stack overlying the highly doped source, comprising:
a high-k dielectric material layer;
a work function metal layer overlying the high-k dielectric material layer; and
a metal gate material overlying the work function metal layer.
11. The semiconductor anti-fuse of claim 10 , further comprising a first metal contact extending partially through the high-k dielectric material.
12. The semiconductor anti-fuse of claim 9 , further comprising a second metal contact extending partially through the highly doped source.