Co-doping process for n-MOS source drain application

1. A method of depositing a layer, comprising:

heating a substrate in a processing chamber to a processing temperature, the substrate having one or more monocrystalline surfaces and one or more non-monocrystalline surfaces;

flowing a processing gas into the processing chamber, the processing gas comprising a halogenated silicon precursor, an arsenic precursor, and a carbon precursor; and

selectively depositing an epitaxial Si:As:C layer on the one or more monocrystalline surfaces, wherein the epitaxial Si:As:C layer comprises a combination of epitaxial Si:As and epitaxial Si:As:C sublayers.

2. The method of claim 1 , wherein at least one of the one or more monocrystalline surfaces comprises silicon and at least one of the one or more non-monocrystalline surfaces comprises a dielectric material.

3. The method of claim 1 , wherein at least a portion of the epitaxial Si:As:C layer has an arsenic concentration of between about 1×10 20 cm −3 and about 2×10 21 cm −3 .

4. The method of claim 1 , wherein the halogenated silicon precursor comprises a chlorinated silane.

5. The method of claim 4 , wherein the chlorinated silane comprises trichlorosilane.

6. The method of claim 5 , wherein the arsenic precursor comprises tertiarybutyl arsine.

7. The method of claim 1 , wherein the carbon precursor is selected from the group consisting of methylsilane, dimethylsilane, ethylsilane, dimethyldisilane, trimethylsilane, hexamethyldisilane, silacyclobutane, methyltrichorosilane, carbon tetrachloride, bromotrichloromethane, and combinations thereof.

8. The method of claim 1 , wherein at least a portion of the epitaxial Si:As:C layer has carbon concentration of between about 1×10 18 cm −3 and about 1×10 21 cm −3 .

9. The method of claim 6 , wherein the processing temperature is between about 400° C. and about 680° C.

10. The method of claim 9 , wherein the epitaxial Si:As:C layer has a thickness between about 2 nm and about 50 nm.

11. A method of depositing a layer, comprising:

heating a substrate in a processing chamber to a processing temperature, the substrate having one or more monocrystalline surfaces and one or more non-monocrystalline surfaces;

flowing a processing gas into the processing chamber, the processing gas comprising a halogenated silicon precursor, an arsenic precursor, and a carbon precursor;

selectively depositing an epitaxial Si:As:C layer on the one or more monocrystalline surfaces; and

depositing an epitaxial silicon layer on the epitaxial Si:As:C layer, the epitaxial silicon layer having an arsenic or phosphorous concentration between 3×10 20 cm −3 and about 5×10 21 cm −3 .

12. A method of forming a device, comprising:

heating a substrate to a processing temperature in a processing chamber, the substrate having one or more features disposed on the substrate, the substrate and the one or more features having at least monocrystalline surfaces and amorphous surfaces;

flowing a gas into the processing chamber, the gas comprising a halogenated silane, an arsenic precursor, and a carbon precursor;

selectively depositing an epitaxial Si:As:C layer on the monocrystalline surfaces; and

selectively depositing an epitaxial silicon based layer on the epitaxial Si:As:C layer, wherein a dopant of the epitaxial silicon based layer comprises arsenic or phosphorous, and wherein a concentration of the dopant in the epitaxial silicon based layer is more than a concentration of arsenic in the epitaxial Si:As:C layer.

13. The method of claim 12 , wherein the halogenated silane comprises trichlorosilane and the arsenic precursor comprises tertiarybutyl arsine.

14. The method of claim 12 , wherein the carbon precursor is selected from the group consisting of methylsilane, dimethylsilane, ethylsilane, dimethyldisilane, trimethylsilane, hexamethyldisilane, silacyclobutane, methyltrichorosilane, carbon tetrachloride, bromotrichloromethane, and combinations thereof.

15. A semiconductor device, comprising:

a substrate;

one or more shallow trench isolation regions defining an active region on the substrate, each of the one or more shallow trench isolation regions comprising a dielectric material;

an undoped monocrystalline feature disposed on the substrate in the active region; and

a first epitaxial silicon layer comprising:

a horizontal portion located on the substrate, the horizontal portion having a first end proximate to one of the one or more shallow trench isolation regions and a second end adjacent to the undoped monocrystalline feature, wherein the first end has a first arsenic concentration and a first carbon concentration at a distance from the substrate; and

a vertical portion normal to the horizontal portion and adjacent to the undoped monocrystalline feature, wherein the vertical portion has a third end adjacent to the second end of the horizontal portion and a fourth end distal to the third end, the fourth end having a second arsenic concentration and a second carbon concentration at a distance from the horizontal portion, wherein the first arsenic concentration and the second arsenic concentration have a variation of less than about 10%, and wherein the first carbon concentration and the second carbon concentration have a variation of less than about 10%.

16. The semiconductor device of claim 15 , wherein at least a portion of the first epitaxial silicon layer has an arsenic concentration between about 1×10 20 cm −3 and about 4×10 21 cm −3 and a carbon concentration of between about 1×10 18 cm −3 and about 1×10 21 cm −3 .

17. The semiconductor device of claim 16 , further comprising a second epitaxial silicon layer on the first epitaxial silicon layer, wherein the second epitaxial silicon layer has a uniform arsenic or phosphorous concentration between 2×10 20 cm −3 and about 5×10 21 cm −3 .

18. The method of claim 1 , wherein at least one of the non-monocrystalline surfaces comprises an amorphous surface.