Integrated circuit with level shifter
A semiconductor die. The die comprises a level shifter coupled to a positive differential input and to a negative differential input comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage coupled to a positive differential output and to a negative differential output, a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and to the positive differential output, a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and to the negative differential output, a positive direct current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output, and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.
1. A semiconductor die, comprising:
a level shifter coupled to a positive differential input and coupled to a negative differential input, comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage at an internal common mode voltage sense node independent of an input common mode voltage of the positive differential input and the negative differential input and where the internal common mode voltage sense node is coupled to a positive differential output and is coupled to a negative differential output;
a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and coupled to the positive differential output;
a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and coupled to the negative differential output;
a positive direct current (DC) feed-forward path coupled to the differential input, coupled to the internal common mode voltage sense node, and coupled to the positive differential output; and
a negative DC feed-forward path coupled to the differential input, coupled to the internal common mode voltage sense node, and coupled to the negative differential output;
a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor coupled in series between a first node coupled to receive the positive differential input and a second node coupled to receive the negative differential input;
wherein the positive DC feed-forward path comprises the third resistor, a seventh resistor, and a second operational amplifier, the second operational amplifier configured as a buffer amplifier having an output coupled to a first lead of the seventh resistor and having a positive input coupled to the third node, the seventh resistor having a second lead coupled to the positive differential output,
and
the negative DC feed-forward path comprises the sixth resistor, an eighth resistor, and a third operational amplifier, the third operational amplifier configured as a buffer amplifier having an output coupled to a first lead of the eighth resistor and having a positive input coupled to the fourth node, the eighth resistor having a second lead coupled to the negative differential output.
2. The semiconductor die of claim 1 , wherein the level shifter comprises:
a first transconductor coupled to a third node connecting the third and fourth resistors and controlled by an output of the operational amplifier; and
a second transconductor coupled to a fourth node connecting the fifth and sixth resistors and controlled by the output of the first operational amplifier.
3. The semiconductor die of claim 2 , wherein the internal common mode voltage sense node is a fifth node connecting the fourth resistor to the fifth resistor.
4. The semiconductor die of claim 2 , wherein the first transconductor and the second transconductor are metal oxide semiconductor (MOS) field effect transistors (FETs).
5. The semiconductor die of claim 1 , wherein semiconductor die is configured to present an input impedance of about 50 ohms to the positive differential input and an input impedance of about 50 ohms to the negative differential input.
6. The semiconductor die of claim 1 , further comprising an input common mode voltage reference that is configured to establish an input common mode voltage of the semiconductor die.
7. A semiconductor die, comprising:
a differential input conditioning stage comprising:
a differential input configured to provide a predefined input impedance and to provide a predefined input common mode voltage,
a level shifter coupled to the differential input and configured to generate an internal common mode voltage at an internal common voltage sense node independent of the predefined input common mode voltage,
a positive alternating current (AC) coupled feed-forward path having a first capacitor coupled to the differential input and coupled to a positive differential output of the differential input conditioning stage,
a negative AC coupled feed-forward path having a second capacitor coupled to the differential input and coupled to a negative differential output of the differential input conditioning stage,
a positive direct current (DC) feed-forward path coupled to the differential input, coupled to the internal common mode voltage sense node, and coupled to the positive differential output of the differential input conditioning stage, and
a negative DC feed-forward path coupled to the differential input, coupled to the internal common mode voltage sense node, and coupled to the negative differential output of the differential input conditioning stage,
and
a data communication processing circuit that is coupled to the positive differential output, coupled to the negative differential output of the differential input conditioning stage, is configured to output a data communication signal;
a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor coupled in series between a first node coupled to receive the positive differential input and a second node coupled to receive the negative differential input;
wherein the positive DC feed-forward path comprises the third resistor, a seventh resistor, and a second operational amplifier, the second operational amplifier configured as a buffer amplifier having an output coupled to a first lead of the seventh resistor and having a positive input coupled to the third node, the seventh resistor having a second lead coupled to the positive differential output, and
the negative DC feed-forward path comprises the sixth resistor, an eighth resistor, and a third operational amplifier, the third operational amplifier configured as a buffer amplifier having an output coupled to a first lead of the eighth resistor and having a positive input coupled to the fourth node, the eighth resistor having a second lead coupled to the negative differential output.
8. The semiconductor die of claim 7 , wherein the data communication processing circuit is configured to receive a signal from the positive differential output and the negative differential output of the differential input conditioning stage with a common mode voltage level associated with the internal common mode voltage reference.
9. The semiconductor die of claim 7 , wherein the data communication processing circuit is a continuous time linear equalizer.
10. The semiconductor die of claim 7 , wherein the data communication processing circuit is a decision feedback equalizer.
11. The semiconductor die of claim 7 , wherein the die comprises 16 interface channels.
12. The semiconductor die of claim 7 , wherein the die comprises 32 interface channels.