Technologies for performing column architecture-aware scrambling

1. A device comprising:

a memory comprising a matrix storing individually addressable bit data, the matrix formed by a plurality of rows and a plurality of columns;

circuitry connected to the memory, wherein the circuitry is implemented at least partly in one or more of configurable hardware circuitry or fixed-functionality hardware circuitry, wherein the circuitry as configured is to:

receive a request to perform a write operation of a plurality of bit values to one of the plurality of columns;

determine a scrambler state at each location in the one of the plurality of columns, the location corresponding to a respective row and column index of the one of the plurality of columns and the scrambler state being indicative of a pattern used to determine a value at the respective column location, wherein to determine the scrambler state at each location comprises to compute a pattern bit of the respective location of the row and column index using a linear function of the row and column index;

scramble each of the bit values as a function of the scrambler state for the respective column location; and

write the scrambled values to each respective column location in the one of the plurality of columns in one mode of operation.

2. The device of claim 1 , wherein the circuitry as configured is further to location traverse down the one of the plurality of columns by advancing a row offset during the write operation in one mode of operation and traverse across one of a plurality of rows by advancing a column offset in a different mode of operation during a second write operation.

3. The device of claim 2 , wherein the circuitry as configured is further to:

receive a request to perform a read operation on the one of the plurality of columns, the request specifying one or more locations in the one of the plurality of columns;

determine the scrambler state at each specified location;

descramble, as a function of the scrambler state, a bit value at each specified location; and

output each bit value in response to the request.

4. The device of claim 1 , wherein to scramble each of the bit values comprises to perform a bitwise operation using the pattern bit and the bit value.

5. The device of claim 4 , wherein to perform the bitwise operation comprises to perform an exclusive-OR operation using the pattern bit and the bit value as input.

6. The device of claim 1 , wherein to determine the scrambler state comprises to advance to a scrambler state for a next location based on the linear function.

7. The device of claim 1 , wherein the memory is of a three-dimensional crosspoint architecture.

8. A system, comprising:

a processor; and

a memory comprising a matrix storing individually addressable bit data, the matrix formed by a plurality of rows and a plurality of columns;

circuitry connected to the memory, wherein the circuitry is implemented at least partly in one or more of configurable hardware circuitry or fixed-functionality hardware circuitry, wherein the circuitry as configured is to:

receive a request to perform a write operation of a plurality of bit values to one of the plurality of columns;

determine a scrambler state at each location in the one of the plurality of columns, the location corresponding to a respective row and column index of the one of the plurality of columns and the scrambler state being indicative of a pattern used to determine a value at the respective column location, wherein to determine the scrambler state at each location comprises to compute a pattern bit of the respective location of the row and column index using a linear function of the row and column index;

scramble each of the bit values as a function of the scrambler state for the respective column location; and

write the scrambled values to each respective column location in the one of the plurality of columns.

9. The system of claim 8 , wherein the circuitry as configured is further to:

receive a request to perform a read operation on the one of the plurality of columns, the request specifying one or more locations in the one of the plurality of columns;

determine the scrambler state at each specified location;

descramble, as a function of the scrambler state, a bit value at each specified location; and

output each bit value in response to the request.

10. The system of claim 8 , wherein to compute the pattern bit of the respective location using the linear function comprises to compute the pattern bit of the respective location using a Galois linear feedback shift register.

11. The system of claim 8 , wherein to scramble each of the bit values comprises to perform a bitwise operation using the pattern bit and the bit value, and wherein to perform the bitwise operation comprises to perform an exclusive-OR operation using the pattern bit and the bit value as input.

12. The system of claim 8 , wherein to determine the scrambler state comprises to advance to a scrambler state for a next location based on the linear function.

13. The system of claim 8 , wherein the memory is of a three-dimensional crosspoint architecture.

14. The system of claim 8 , wherein the memory is in a data storage device.

15. The system of claim 8 , wherein the memory is in a memory device.

16. A method comprising:

receiving, by a device having a memory, a request to perform a read operation to memory, wherein the memory comprises a matrix storing individually addressable bit data, wherein the matrix is formed by a plurality of rows and a plurality of columns, and wherein the read operation specifies to read a plurality of bit values from one of the plurality of columns;

determining, by the device, a scrambler state at each location in the one of the plurality of columns, the location corresponding to a respective row and column index of the one of the plurality of columns and the scrambler state being indicative of a pattern used to determine a value at the respective column location, wherein determining the scrambler state at each location comprises computing a pattern bit of the respective location of the row and column index using a linear function of the row and column index;

descrambling, by the device, each of the bit values as a function of the scrambler state for the respective column location; and

reading, by the device, the descrambled values from each respective column location in the one of the plurality of columns.

17. The method of claim 16 , wherein the memory is of a three-dimensional crosspoint architecture.

18. One or more machine-readable storage media storing instructions, which, when executed on a processor, causes a device having a memory to:

receive a request to perform a read operation to memory, wherein the memory comprises a matrix storing individually addressable bit data, wherein the matrix is formed by a plurality of rows and a plurality of columns, and wherein the read operation specifies to read a plurality of bit values from one of the plurality of columns;

determine a scrambler state at each location in the one of the plurality of columns, the location corresponding to a respective row and column index of the one of the plurality of columns and the scrambler state being indicative of a pattern used to determine a value at the respective column location, wherein to determine the scrambler state at each location comprises to compute a pattern bit of the respective location of the row and column index using a linear function of the row and column index;

descramble each of the bit values as a function of the scrambler state for the respective column location; and

read the descrambled values from each respective column location in the one of the plurality of columns.